std_logic Allowed Values - 2022.1 English

Vivado Design Suite User Guide: Synthesis (UG901)

Document ID
UG901
Release Date
2022-06-06
Version
2022.1 English
Table 5-2:      std_logic Allowed Values

Value

Meaning

What Vivado synthesis does

U

initialized

Not accepted by Vivado synthesis

X

unknown

Treated as don’t care

0

low

Treated as logic zero

1

high

Treated as logic one

Z

high impedance

Treated as high impedance

W

weak unknown

Not accepted by Vivado synthesis

L

weak low

Treated identically to 0

H

weak high

Treated identically to 1

-

don’t care

Treated as don’t care