Module Instantiation - 2022.1 English

Vivado Design Suite User Guide: Synthesis (UG901)

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2022.1 English

A behavioral Verilog module instantiation statement does the following:

Defines an instance name.

Contains a port association list. The port association list specifies how the instance is connected in the parent module. Each element of the port association list ties a formal port of the module declaration to an actual net of the parent module.

Is instantiated in another module. See the following coding example.