Multipliers - 2022.1 English

Vivado Design Suite User Guide: Synthesis (UG901)

Document ID
Release Date
2022.1 English

Vivado synthesis infers Multiplier macros from multiplication operators in the source code. The resulting signal width equals the sum of the two operand sizes. For example, multiplying a 16-bit signal by an 8-bit signal produces a result of 24 bits.


RECOMMENDED:   If you do not intend to use all most significant bits of a device, Xilinx recommends that you reduce the size of operands to the minimum needed, especially if the Multiplier macro is implemented on slice logic.