Implementation on FPGA - 2024.2 English

Vitis Libraries

Document ID
XD160
Release Date
2024-11-29
Version
2024.2 English

XTS-AES128 and XTS-AES256 modes are supported in this implementation.

Attention

The bit-width of the interfaces provided is shown as follows:

  plaintext ciphertext cipherkey IV textlength
CBC-AES128 128 128 128 128 64
CBC-AES256 128 128 256 128 64

The algorithm flow chart is shown as follows:

algorithm flow chart of XTS

As seen from the chart, the dependency of XTS encryption flow only exists between the first block and the second to last block. It is same as shown in the XTS decryption flow. Therefore, the initiation interval (II) of XTS encryption and decryption mode can achieve 1. One one-word AES encryption module is instanced in XTS decryption.