The AMD Vitis™ digital signal processing library (DSPLib) provides an implementation of different L1/L2/L3 elements for digital signal processing.
The DSPLib contains:
PL DSP Library
The AMD Vitis Programmable Logic (PL) DSP library consists of an implementation of a Discrete Fourier Transform using a fast Fourier transform (FFT) algorithm for acceleration on AMD Adaptive Engineering FPGAs. The library is planned to provide three types of implementations, namely L1 PL primitives, L2 PL kernels, and L3 software APIs. Those implementations are organized in hardware (hw) sub-directories of the corresponding L1, L2, and L3.
The L1 PL primitives can be leveraged by developers working on hardware design implementation or designing hardware kernels for acceleration. They are particularly suitable for hardware designers. The L2 PL kernels are HLS-based predesigned kernels that can be directly used for FPGA acceleration of different applications on integration with XRT. The L3 provides software APIs in C, C++, and Python which allow software developers to offload FFT calculation to FPGAs for acceleration. Before an FPGA can perform the FFT computation, the FPGA needs to be configured with a particular image called an overlay.
The Vitis PL DSP Library provides a fully synthesizable PL based Super Sample data Rate (SSR) FFT, as well as a 2-Dimensional FFT version. For detailed documentation, refer to 1-Dimensional(Line) SSR FFT L1 FPGA Module and 2-Dimensional(Matrix) SSR FFT L1 FPGA Module.
AI Engine DSP Library
The AMD Vitis AIE DSP library consists of designs of various DSP algorithms, optimized to take full advantage of the processing power of AMD Versal™ Adaptive SoC devices, which contain an array of AI Engines high-performance vector processors.
The library is organized into three parts:
- L1 AIE kernels
- L2 AIE graphs and VSS Makefiles
- L3 software APIs
Currently, there are no L3 software APIs, and the recommended entry point for all library elements is an L2 AIE graph.
For more information, refer to Introduction for AIE DSP library.
The Vitis AIE DSP Library provides a SSR FFT implementation targeting AIE, as well as various SSR Finite Impulse Response (FIR) filters, SSR Direct Digital Synthesis (DDS), and General Matrix Multiply (GeMM) implementation. For a full list of available DSP functions, refer to DSP Library Functions.
Introduction
L1 PL DSP Library User Guide
L2 AIE DSP Library User Guide
- Introduction
- DSP Library Functions
- Configuration
- Compiling and Simulating
- Library Element Unit Test
- Compiling Using the Makefile
- Troubleshooting Compilation
- Power Analysis
- Library Element Configuration Parameters
- Common Configuration Parameters
- Bitonic Sort configuration parameters
- Convolution / Correlation configuration parameters
- DDS/Mixer Configuration Parameters
- DFT Configuration Parameters
- FFT Configuration Parameters
- FFT Window Configuration Parameters
- FIR Configuration Parameters
- Function Approximation configuration parameters
- Hadamard Product configuration parameters
- Kronecker configuration parameters
- Matrix Multiply Configuration Parameters
- Matrix Vector Multiply Configuration Parameters
- Mixed Radix FFT Configuration Parameters
- Outer Tensor configuration parameters
- Sample Delay Configuration Parameters
- Widgets Configuration Parameters
- Benchmark/QoR