Resource Utilization - 2024.2 English - XD160

Vitis Libraries

Document ID
XD160
Release Date
2024-11-29
Version
2024.2 English

The hardware resources are listed in Table 181. This is for the demonstration as configured by default (two cfB76Engine engines) achieving a 300 MHz clock rate.

Table 181 Hardware resources for single kernel with two parallel cfB76Engine engines.
Engines BRAM DSP Register LUT Latency clock period(ns)
b76_kernel 374 496 77741 65491 334 3.333