Implementation on FPGA - 2024.2 English

Vitis Libraries

Release Date
2024-11-29
Version
2024.2 English

CTR-AES128, CTR-AES192, and CTR-AES256 modes are supported in this implementation.

Attention

The bit-width of the interfaces provided is shown as follows:

  plaintext ciphertext cipherkey IV
CTR-AES128 128 128 128 128
CTR-AES192 128 128 192 128
CTR-AES256 128 128 256 128

The algorithm flow chart is shown as follows:

algorithm flow chart of CTR

As seen from the chart, both encryption and decryption parts of CTR mode have no dependencies, so the input block of each iteration can be directly calculated by the counter. Thus, both encryption and decryption part of CTR mode can achieve an initiation interval (II) = 1.