Implemention - 2024.2 English - XD160

Unlike common L1 primitives, the hardware regex-VM is not using a stream-based interface due to the characteristic of the virtual machine (VM) approach. Thus, the dataflow tricks utilized in the kernel level cannot be like the one commonly used in the L2 implementation. Detailed explanations are provided here.

For the common stream-based dataflow, you want the interfaces between modules as FIFOs, and this is the reason why you find that the interfaces of L1 primitives are usually defined as hls::stream. By implementing the interface as FIFOs, these connected modules works as systolic array when dataflow region applied to them. A consumer in the stream-based dataflow region goes on only if the producer before it gives a data to its input FIFO. Thus, it is not necessary for you to switch the module on or off manually.

However, for those primitives with buffer interfaces like regex-VM, it comes to a ping-pong buffer structure when the dataflow pragma is applied to it. Because you have no empty signal as FIFO provided in the buffer-based dataflow region, you have to control the modules manually to avoid malfunctioning on the pipeline. This can be explained as follows; suppose you have an input log which the messages within it needs N rounds to be all fed into the buffers of each PU in reEngineKernel:

Operation	Round 0	Round 1	Round 2	…	Round N - 1	Round N	Round N + 1
Feeding buffers	Yes	Yes	Yes	…	Yes	No	No
Executing matcher	No	Yes	Yes	…	Yes	Yes	No
Collecting results	No	No	Yes	…	Yes	Yes	Yes

You will not have a N + 2 round, as the whole pipeline finished right after round N + 1.