Implementation on FPGA - 2024.2 English

Vitis Libraries

Document ID
XD160
Release Date
2024-11-29
Version
2024.2 English

For \(s1\), its calculation process is simple and does not affect performance, so there is no explanation for implementation. Refer to the code directly for details.

\[s1=(1+B_{0}+B_{1}+\cdots +B_{n-1})%65521\]

For \(s2\), it can be expressed as

\[s2=((1+B_{0})+(1+B_{0}+B_{1})+\cdots +(1+B_{0}+B_{1}+\cdots +B_{n-1}))%65521\]

Where B is the input date for which the checksum is to be calculated, and n is its size in byte.

In code, the process is as follows:

  1. Initialize \(s1=1\) and \(s2=0\), set \(i=0\).
  2. calcute \(tmp[0]=B[i],tmp[i]=B[i+1],\cdots,tmp[W-1]=B[i+W-1]\).
  3. calcute \(s1+=tmp[0]\) and \(s2=s1*W+tmp[0]+tmp[i]+\cdots +tmp[W-1]\), and ensure that \(s1\) and \(s2\) are less than 65521.
  4. set \(i+=W\), if \(i<size\), go to step 2, otherwise end.

For more information, check out source code.