Implementation on FPGA - 2024.2 English - XD160

Vitis Libraries

Document ID
XD160
Release Date
2024-11-29
Version
2024.2 English

The internal structure of SHA-3 algorithms is seen in the following figures:

Structure of SHA-3 algorithms Structure of SHAKE algorithms

As seen from the figures, hash calculation in both SHA-3 and SHAKE is much different from SHA-1 and SHA-2. Since the internal state array is updated iteratively (by the input message) and used in the next permutation, it cannot be partitioned into block generation part and digest part.

Both the digest parts of SHA-3 and SHAKE pad or split the input message into fixed sized blocks (1600-bit for each), and XOR it to the state array of the last iteration.

The message word size is 64-bit for both SHA-3 and SHAKE, and each block has a different number of message words according to the specific suffix of the algorithm which is selected. The number can be defined as:

\[NumMsgWord = \frac{200 - \frac{Suffix}{4}}{8}\]

Loop-carried dependency is enforced by the algorithm, and thus the digest part cannot reach II=1.