Implementation on FPGA - 2024.2 English - XD160

Vitis Libraries

Document ID
XD160
Release Date
2024-11-29
Version
2024.2 English

The internal structure of SHA-1 is shown in the following figure:

Structure of SHA-1

As seen from the figures, the hash calculation can be partitioned into two parts.

  • The pre-processing part pads or splits the input message, which is comprised by a stream of 32-bit words into fixed sized blocks (512-bit for each).
  • The digest part iteratively computes the hash values. Loop-carried dependency is enforced by the algorithm itself, thus this part cannot reach an initiation interval (II) = 1.

As the two parts can work independently, they are designed into parallel dataflow process, connected by streams (FIFOs).