Performance - 2024.2 English

Vitis Libraries

Document ID
XD160
Release Date
2024-11-29
Version
2024.2 English

To represent the resource utilization in each benchmark, separate the overall utilization into two parts, where P stands for the resource usage in platform, that is those instantiated in static region of the FPGA card. K represents those used in kernels (dynamic region). The input is matrix, and the target device is set to AMD Alveo™ U250.

Table 190 Performance for processing quantitative_finance on FPGA
Architecture Kernels Latency(s) Timing LUT(P/K) BRAM(P/K) URAM(P/K) DSP(P/K)
MCEuropeanEngine(U250) 4 25.94 300MHz 108.1K/21.1K 178/127 0/20 4/2
MCAmericanEngineMultiKernel(U250) 3 1.811 280MHz 101.7K/101.5K 165/387 0/112 4/3
TreeEngine(U250) TreeCallableEngineHWModel 1 3.484 275MHz 101.7K/160.5K 165/523.5 0/110 4/6
TreeCapFloorEngineHWModel 1 3.484 275MHz 101.7K/160.5K 165/523.5 0/110 4/6
TreeSwapEngineHWModel 1 3.484 275MHz 101.7K/160.5K 165/523.5 0/110 4/6
TreeSwaptionEngineBKModel 1 3.484 275MHz 101.7K/160.5K 165/523.5 0/110 4/6
TreeSwaptionEngineCIRModel 1 3.484 275MHz 101.7K/160.5K 165/523.5 0/110 4/6
TreeSwaptionEngineECIRModel 1 3.484 275MHz 101.7K/160.5K 165/523.5 0/110 4/6
TreeSwaptionEngineG2Model 1 3.484 275MHz 101.7K/160.5K 165/523.5 0/110 4/6
TreeSwaptionEngineHWModel 1 3.484 275MHz 101.7K/160.5K 165/523.5 0/110 4/6
TreeSwaptionEngineVModel 1 3.484 275MHz 101.7K/160.5K 165/523.5 0/110 4/6
SVD(U250) 1 0.000196 300MHz 101.7K/40.3K 165/9 0/0 4/126

These are the details for benchmark result and usage steps.