Implementation on FPGA - 2024.2 English - XD160

Vitis Libraries

Document ID
XD160
Release Date
2024-11-29
Version
2024.2 English

CBC-DES, CBC-AES128, CBC-AES192, and CBC-AES256 modes are supported in this implementation.

Attention

The bit-width of the interfaces we provide is shown as follows:

  plaintext ciphertext cipherkey IV
CBC-DES 64 64 64 64
CBC-AES128 128 128 128 128
CBC-AES192 128 128 192 128
CBC-AES256 128 128 256 128

The algorithm flow chart is shown as follows:

algorithm flow chart of CBC

As seen from the chart, the encryption part of CBC mode has loop-carried dependency, which is enforced by the algorithm, then the input block of each iteration (except for iteration 0) needs a feedback data from its last iteration. Thus, the initiation interval (II) of CBC encryption cannot achieve an II = 1. However, the decryption part of CBC mode has no dependencies, so that it can achieve an II = 1.