Super Sample Rate - Sample to Port Mapping - 2023.2 English

Vitis Libraries

Release Date
2023-12-20
Version
2023.2 English
When Super Sample Rate operation is used, data is input and output using multiple ports. These multiple ports on input or output act as one channel.
The input data channel must be split over multiple ports where each successive input sample is sent to a different input port in a round-robin fashion, i.e. sample 0 goes to input port in[0], sample 1 to in[1], etc up to N-1 where N=TP_SSR, then sample N goes to in[0], sample N+1 goes to in[1] and so on.
Output samples are output from the multiple output ports in the same fashion.
In addition, where TP_DUAL_IP is also enabled, there will be two sets of SSR input ports, in and in2, where data must be organized in 128-bit interleaved pattern.
Allocate samples to ports 0 to N-1 of port in in the round-robin fashion above until each port has 128-bits of data, then allocate the next samples in a round-robin fashion to ports 0 through N-1 of port in2 until these have 128-bits of data, then return to allocating samples to ports 0 through N-1 of in, and repeat.

For example, if we have a data stream like int32 x = 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, ..., then an SSR of 3 with dual input ports would look like the below:

in[0] = 0, 3, 6, 9, 24, 27, 30, 33, ...
in[1] = 1, 4, 7, 10, 25, 28, 31, 34, ...
in[2] = 2, 5, 8, 11, 26, 29, 32, 35, ...
in2[0] = 12, 15, 18, 21, 36, 39, 42, 45, ...
in2[1] = 13, 16, 19, 22, 37, 40, 43, 46, ...
in2[2] = 14, 17, 20, 23, 38, 41, 44, 47, ...
The output data will be produced in a similar method.
Samples will be sent to each port in a round-robin fashion, in addition being organized in 128-bit interleaved patterns when 2 output ports are in use, i.e. when TP_NUM_OUTPUTS is set to 2.