Implementation - 2024.1 English

Vitis Libraries

Release Date
2024.1 English

The algorithm implementation is shown in the following figure:

Figure 1 LabelPropagation architecture on FPGA

As seen from the figure:

  1. Module Convert_CSR_CSC: convert compressed sparse row (CSR) format graph to compressed sparse column (CSC) format graph, When the iterNum is small, the module accounts for a large proportion of the total execution time of the LP_Kernel. The execution time of the module is reduced by increasing the cache depth.
  2. Module getLabel and its previous module: get all labels of all neighbors of vertex u.
  3. Module HashMaxFreq and labelSelect: find the highest frequency label (Select a label at random if there are multiple highest frequency labels), then output to DDR.