Multiple Buffer Ports - 2023.2 English

Vitis Libraries

Release Date
2023-12-20
Version
2023.2 English

Note

AIE-ML devices only support single input/output port.

Multiple input ports

Symmetric FIRs, including half-band FIRs, can be configured with 2 input buffers. Such implementation is a trade-off between performance and resource utilization. Symmetric FIRs with 2 input ports avoid the potential for memory read contention, which would otherwise result in stall cycles and therefore lower throughput.

Set TP_DUAL_IP template parameter to 1, to create a FIR kernel with 2 input buffer ports. In this scenario, FIR kernel with 2 input ports will be created where FIR kernel expects each buffer to contain exact copy of the same data. Both input ports should be connected to the same data source through the FIR’s graph.

Multiple output ports

All FIRs can be configured with 2 output buffers. Such design allows greater routing flexibility that offers buffers to be connected directly to downstream components for further processing avoiding a costly and limiting broadcast with a stream.

Set TP_NUM_OUTPUTS template parameter to 2, to create a FIR kernel with 2 output buffer ports. In this scenario, two exact copies of output data will be produced in two independent memory buffers.

For example, a single-rate FIR with a 512 input sample buffer will produce 2 output buffers, where each buffer is 512 samples.