Implementation - 2024.2 English - XD160

Vitis Libraries

Document ID
XD160
Release Date
2024-11-29
Version
2024.2 English

The detail algorithm implementation is illustrated below:

Diagram of Connected Component

The overall diagram of this kernel is mostly same as BFS kernel except for extra input CSC graph and one mergeSort module. The mergeSort merges and outputs one sorted stream for two input indegree and outdegree sorted stream. And the duplicate vertex in the single sorted output stream is removed before entering the readRes module.