Transfer of Completions with Data - 3.4 English

Versal Adaptive SoC CPM Mode for PCI Express Product Guide (PG346)

Document ID
PG346
Release Date
2024-05-30
Version
3.4 English

In the Dword-aligned mode, the transfer starts with the three descriptor Dwords, followed immediately by the payload Dwords. The entire TLP, consisting of the descriptor and payload, is transferred as a single AXI4-Stream packet. Data within the payload is always a contiguous stream of bytes when the length of the payload exceeds two Dwords. The positions of the first valid byte within the first Dword of the payload and the last valid byte in the last Dword can then be determined from the Lower Address and Byte Count fields of the Request Completion Descriptor. When the payload size is 2 Dwords or less, the valid bytes in the payload are not be contiguous. In these cases, the user logic must store the First Byte Enable and the Last Byte Enable fields associated with each request sent out on the requester request interface and use them to determine the valid bytes in the completion payload. The user logic are optionally use the byte enable outputs byte_en[63:0] within the m_axi_rc_tuser bus to determine the valid bytes in the payload, in the cases of both contiguous and non-contiguous payloads.

The core keeps the signal m_axis_rc_tvalid asserted over the entire duration of the packet. The user logic can prolong a beat at any time by pulling down m_axis_rc_tready. The AXI4-Stream interface signals m_axis_rc_tkeep (one per Dword position) indicate the valid Dwords in the packet including the descriptor and any null bytes inserted between the descriptor and the payload. That is, the tkeep bits are set to 1 contiguously from the first Dword of the descriptor until the last Dword of the payload. During the transfer of a packet, the m_axis_rc_tkeep bits can be 0 only in the last beat of the packet, when the packet does not fill the entire width of the interface. The signal m_axis_rc_tlast is always asserted in the last beat of the packet.

The m_axi_rc_tuser bus provides several optional signals that can be used to simplify the logic associated with the user side of the interface, or to support additional features. The signal is_sop[0] is asserted in the first beat of every packet, when its descriptor is on the bus. When the straddle option is not in use, none of the other sop and eop indications within m_axi_rc_tuser are relevant to the transfer of Completions. The byte enable outputs byte_en[127:0] (one per byte lane) indicate the valid bytes in the payload. These signals are asserted only when a valid payload byte is in the corresponding lane (it is not asserted for descriptor or null bytes). The asserted byte enable bits are always contiguous from the start of the payload, except when payload size is 2 Dwords or less. For Completion payloads of two Dwords or less, the 1s on byte_en are not be contiguous. Another special case is that of a zero-length memory read, when the core transfers a one-Dword payload with the byte_en bits all set to 0. Thus, the user logic can, in all cases, use the byte_en signals directly to enable the writing of the associated bytes into memory.

The following figure illustrates the Dword-aligned transfer of a Completion TLP received from the link with an associated payload across the requester completion interface. For the purpose of illustration, the size of the data block being written into user memory is assumed to be n Dwords, where n = k*16 + 4, for some k > 1. The timing diagrams in this section assume that the Completions are not straddled on the interface. The straddle feature is described in Straddle Option for RC Interface.

Figure 1. Transfer of a Completion with Data on the Requester Completion Interface (Dword-Aligned Mode)

The following figure illustrates the address-aligned transfer of a Completion TLP received from the link with an associated payload across the requester completion interface. In the example timing diagrams, the starting Dword address of the data block being transferred (as conveyed in the Lower Address field of the descriptor) is assumed to be (m*16 +1), for some integer m. The size of the data block is assumed to be n Dwords, where n = k * 16 +4, for some k > 0. The straddle option is not valid for 128-bit address aligned transfers, so the timing diagrams assume that the Completions are not straddled on the interface.

In the 128-bit address aligned mode, the delivery of the payload always starts in the beat following the last byte of the descriptor. The first byte of the payload can appear on any of the bytes lanes 16 - 32, based on the address of the first valid byte of the payload. The m_axis_rc_tkeep bits are set to 1 contiguously from the first Dword of the descriptor until the last Dword of the payload. The alignment of the first Dword on the data bus within its 128-bit field is determined by the setting of the addr_offset[1:0] input of the requester request interface when the user application sent the request to the core. The user application are optionally use the byte enable outputs byte_en[127:0] to determine the valid bytes in the payload.

Figure 2. Transfer of a Completion with Data on the Requester Completion Interface (128-bit Interface, Address Aligned Mode)