Customizing and Generating the CIPS IP Core for CPM5 - 3.4 English

Versal Adaptive SoC CPM Mode for PCI Express Product Guide (PG346)

Document ID
PG346
Release Date
2024-05-30
Version
3.4 English

This section includes information about using the AMD Vivado™ Design Suite to customize and generate the Control, Interfaces and Processing System IP core. This section configures the CIPS IP core to access the CPM PCIe controllers directly. For extended information about the CIPS IP core, see the Control, Interface and Processing System LogiCORE IP Product Guide (PG352).