Ports - 3.4 English

Versal Adaptive SoC CPM Mode for PCI Express Product Guide (PG346)

Document ID
PG346
Release Date
2024-05-30
Version
3.4 English

New Ports

All of the ports in the CPM5 PCIE have pcie0 or pcie1 (as per the core selected ) as prefix to the port names used in AMD UltraScale+™ . For example, for the s_axis_rq_tuser port in UltraScale+ is pcie0_s_axis_rq_tuser in AMD Versal™ CPM5.

The following table lists the new ports in the Versal CPM5 Controllers relative to the UltraScale+ device integrated block for PCIe IP.

Note: The following tables mentions only pcie0* ports, but apply to both pcie0* and pcie1* ports.
Table 1. New Ports for Versal CPM5
Name I/O Notes
pcie0_cfg_status_10b_tag_requester_enable[3:0] O Per function state of Device Control2 Register 10-Bit Tag Requester Enable bit.
pcie0_cfg_status_atomic_requester_enable[3:0] O Per function state of Device Control2 Register AtomicOp Requester Enable bit.
pcie0_cfg_ats_control_enable[3:0] O Per function State of ATS Control Register Enable bit.
pcie0_cfg_status_ext_tag_enable O State of Device Control Register Ext Tag (8-Bit) Enable bit.
pcie0_cfg_fc_vc_sel I Selects the Virtual Channel for the type of flow control information presented on the cfg_fc_* signals.
pcie0_cfg_vc1_enable O VC1 Resource Control Register: VC Enable bit.
pcie0_cfg_vc1_negotiation_pending O VC1 Resource Status Register: VC Negotiation Pending bit.
pcie0_cfg_status_pasid_enable[3:0] O Per Function PASID Enable.
pcie0_cfg_status_pasid_exec_permission_enable[3:0] O Per Function PASID Exec Permission Enable.
pcie0_cfg_status_pasid_privil_mode_enable[3:0] O Per Function PASID Privil Mode Enable.
pcie0_cfg_fc_ph_scale[1:0] O Please refer to port list for details.
pcie0_cfg_fc_pd_scale[1:0] O Please refer to port list for details.
pcie0_cfg_fc_nph_scale[1:0] O Please refer to port list for details.
pcie0_cfg_fc_npd_scale[1:0] O Please refer to port list for details.
pcie0_cfg_fc_cpld_scale[1:0] O Please refer to port list for details.
pcie0_cfg_fc_cplh_scale[1:0] O Please refer to port list for details.
pcie0_cfg_status_wrreq_flr_vld O

Configuration Write Request FLR Valid:

Shows a 1-cycle pulse when a CfgWr Request TLP to the FLR bit field is received from the PCI Express link.
pcie0_cfg_status_wrreq_msi_vld O

Configuration Write Request MSI Valid:

Shows a 1-cycle pulse when a CfgWr Request TLP to the MSI bit field is received from the PCI Express link.
pcie0_cfg_status_wrreq_msix_vld O

Configuration Write Request MSIX Valid:

Shows a 1-cycle pulse when a CfgWr Request TLP to the MSIX bit field is received from the PCI Express link.
pcie0_cfg_status_wrreq_bme_vld O

Configuration Write Request BME / Interrupt Disable Valid:

Shows a 1-cycle pulse when a CfgWr Request TLP to either the BME bit field or the Interrupt Disable bit field is received from the PCI Express link.
pcie0_cfg_status_wrreq_vfe_vld O

Configuration Write Request VFE Valid:

Shows a 1-cycle pulse when a CfgWr Request TLP to the VF Enable bit field is received from the PCI Express link.
pcie0_cfg_status_wrreq_function_number[15:0] O

Configuration Write Request Function Number:

Shows the Function ID for 1 cycle corresponding to the wrreq valid when a CfgWr Request TLP is received from the PCI Express link.
pcie0_cfg_status_wrreq_out_value[3:0] O

Configuration Write Request Output Value:

Shows a 1-cycle pulse of the value corresponding to the wrreq valid when a CfgWr Request TLP is received from the PCI Express link.

  • When FLR-Vld is asserted:
    • [0]: flr value
  • When MSI-Vld is asserted:
    • [3:1]: msi_mmenable[2:0] value
    • [0]: msi_enable value
  • When BME-Vld is asserted:
    • [3]: interrupt_disable write byte enable
    • [2]: interrupt_disable value
    • [1]: bus_master_enable write byte enable
    • [0]: bus_master_enable value
  • When VFE-Vld is asserted:
    • [0]: vf_enable value
  • When MSIX-Vld is asserted:
    • [1]: msix_mask value
    • [0]: msix_enable value
pcie0_cfg_status_per_function_out[23:0] O

Per-Function Output: Status.

[0] Bus Master Enable

[1] MSIX Enable

[2] MSIX Mask

[3] Transactions Pending

[4] FLR In Progress

[5] ATS Control

[8:6] For PF: Power State[2:0]

[9] For PF: Memory Space Enable

[10] For PF: 10-Bit Tag Requester Enable

[11] For PF: MSI Enable

[14:12] For PF: MSI mmenable[2:0]

[15] For PF: IO Space Enable

[16] For PF: INTx Disable

[17] For PF: RCB Status

[18] For PF: Atomic Requester Enable

[19] For PF: PASID Enable

[20] For PF: PASID Exec Permission Enable

[21] For PF: PASID Privil Mode Enable

[23:22] For PF: PRI Control

pcie0_cfg_status_per_function_vld O

Per-Function Output Valid:

When asserted, indicates the Per-Function Input Request has been received and the cfg_perfunc_out contains valid output data.
pcie0_cfg_control_per_function_number[15:0] I

Per-Function Function ID Input Request:

Valid entries 16'h0000-16'h100F for Function IDs from 0 to 15 (PFs) and 16 to 4111 (VFs). Values 16'h1010-16'hFFFF are reserved.
pcie0_cfg_control_per_function_req I

Per-Function Input Request:

The user application asserts this input to request status of the cfg_perfunc_func_num Function ID. This input must be held asserted until cfg_perfunc_vld is asserted indicating the request has been received.

Port Changes

The following table lists the ports for which the widths were changed in the Versal CPM5 Controllers relative to the UltraScale+ device integrated block for PCIe IP.

Table 2. Port Width Changes For Current Ports
Name I/O
pcie0_cfg_status_rq_tag0[9:0] O
pcie0_cfg_status_rq_tag1[9:0] O
Note: The above mentioned port width changes does not include 1024-bit interface.

Ports Not Available

The following table lists the ports which were deprecated in the Versal CPM5 Controllers relative to the UltraScale+ device integrated block for PCIe IP.

Table 3. Deprecated Ports
Name I/O Notes
cfg_pm_aspm_l1_entry_reject I Now part of the register table.
cfg_pm_aspm_tx_l0s_entry_disable I Now part of the register table.
cfg_config_space_enable I Now part of the register table.
cfg_dsn I Now part of the register table.
cfg_dev_id_pf0 I Now part of the register table.
cfg_dev_id_pf1 I Now part of the register table.
cfg_dev_id_pf2 I Now part of the register table.
cfg_dev_id_pf3 I Now part of the register table.
cfg_vend_id I Now part of the register table.
cfg_rev_id_pf0 I Now part of the register table.
cfg_rev_id_pf1 I Now part of the register table.
cfg_rev_id_pf2 I Now part of the register table.
cfg_rev_id_pf3 I Now part of the register table.
cfg_subsys_id_pf0 I Now part of the register table.
cfg_subsys_id_pf1 I Now part of the register table.
cfg_subsys_id_pf2 I Now part of the register table.
cfg_subsys_id_pf3 I Now part of the register table.
cfg_subsys_vend_id I Now part of the register table.
cfg_ds_port_number I Now part of the register table.
cfg_ds_bus_number I Now part of the register table.
cfg_ds_device_number I Now part of the register table.
cfg_ds_function_number I Now part of the register table.
cfg_link_training_enable I Now part of the register table.
cfg_req_pm_transition_l23_ready I Now part of the register table.
cfg_bus_number I Now part of the register table.
cfg_dpa_substate_change O Not available
cfg_obff_enable O Not available
phy_rdy_out O Not available
sys_reset I Reset now routed via PS.