Clock and Reset Interface - 3.4 English

Versal Adaptive SoC CPM Mode for PCI Express Product Guide (PG346)

Document ID
PG346
Release Date
2024-05-30
Version
3.4 English

Fundamental to the operation of the core, the Clock and Reset interface provides the system-level clock and reset to the core as well as the user application clock and reset signal. The table below defines the ports in the Clock and Reset interface of the core.

The pcie(n)_user_clk signal is the clock available in the fabric region. For more information on clock and reset interface, refer to Clocking and Resets in Designing with the Core chapter.

Note: The pcie0* signals map to PCIe Controller 0, and pcie1* signals map to PCIe Controller 1 in the port descriptions below.
Table 1. Clock and Reset Interface Port Descriptions
Port I/O Width Description

pcie0_user_clk
pcie1_user_clk

O 1 User clock output (62.5, 125, or 250 MHz)

This clock has a fixed frequency and is configured in the AMD Vivado™ Integrated Design Environment (IDE).

pcie0_user_reset
pcie1_user_reset

O 1 This signal is deasserted synchronously with respect to pcie(n)_user_clk. It is asserted asynchronously with perst assertion.