Port Descriptions - 3.4 English

Versal Adaptive SoC CPM Mode for PCI Express Product Guide (PG346)

Document ID
PG346
Release Date
2024-05-30
Version
3.4 English
Note: All the ports in the description field of the table excludes pcie0/pcie1 appended to the port names as the description is same for both. Please note that the pcie0* port name maps to pcie0* port names in the description field and pcie1* port name maps to pcie1* port names in the description field.

For example, the description for pcie0_m_axis_cq_tuser and pcie1_m_axis_cq_tuser states that these signals are valid when m_axis_cq_tvalid is high. Here, pcie0_m_axis_cq_tuser is valid when pcie0_m_axis_cq_tvalid is high, and pcie1_m_axis_cq_tuser is valid when pcie1_m_axis_cq_tvalid is high.