Known Issues and Limitations - 3.4 English

Versal Adaptive SoC CPM Mode for PCI Express Product Guide (PG346)

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3.4 English
  • Engineering Silicon (ES) is not supported for VC1902, VC1802, and VM1802 devices. Only production silicon is supported for these devices.
  • PCIe features that are incompatible with Tandem Configuration:
    • PCIe Extended Configuration Space, as this requires PL logic.
    • QDMA multifunction is not supported. This feature uses PL mailbox which is probed during the driver load.
  • Stage 1 and stage 2 PDI images must remain linked. If you update one, update the other to ensure both stages are generated from the same implemented design.
  • Do not reload the same or a new stage 2 image on the fly. Isolation circuitry on the periphery of the CPM is designed to ensure safe operation of the PCI Express endpoints prior to the rest of the device becoming active. Upon stage 2 completion, the isolation is released and it is not re-enabled for a dynamic reload of the stage 2 image.
  • For the Versal architecture, CPM Tandem PROM configuration can be used with post configuration flash update. This is different from previous (UltraScale+ and older) architectures that did not support Tandem PROM post configuration flash update. Given the lack of dual-mode configuration pins, there is no PERSIST requirement to keep a configuration port active.
  • At this point there is no Tandem with Field Updates predefined use case. You can create a Tandem + DFX solution noted above where both features are enabled in the same design, but creation of the design hierarchy and floor plan as well as insertion of any decoupling logic are the responsibility of the designer. The dynamic (DFX) portion of the solution would be limited to programmable logic and NoC resources, and not parts of the Scalar Engines (processors).
  • The CPM itself (and therefore Tandem Configuration) is not compatible with the Classic SoC Boot flow, which uses DFX to separate PS and PL configuration events. This is because the CPM solution requires soft logic for most configurations and thus the DFX region cannot be constructed to include all of the programmable logic.
  • No support is planned for Tandem Configuration for PL-based PCIe sites. The complexity and inefficiency of such a solution in Versal device makes it very difficult to meet the 120 ms goal for Tandem PROM and impossible for Tandem PCIe. If compliant link training is a fundamental requirement, be sure to use a device with the CPM and enable the Tandem feature within CIPS customization.