Name | I/O | Width | Description |
---|---|---|---|
pcie0_m_axis_rc_tdata pcie1_m_axis_rc_tdata | O | 1024 | Transmit data from the PCIe requester completion interface to the user application. |
pcie0_m_axis_rc_tuser pcie1_m_axis_rc_tuser | O | 337 | This is a set of signals containing sideband information for the TLP being transferred. These signals are valid when pcie(n)_m_axis_rc_tvalid is High. The individual signals in this set are described in the following table. |
pcie0_m_axis_rc_tlast pcie1_m_axis_rc_tlast | O | 1 | The core asserts this signal in the last beat of a packet to indicate the end of the packet. When a TLP is transferred in a single beat, the core sets this bit in the first beat of the transfer. This output is used only when the straddle option is disabled. When the straddle option is enabled, the core sets this output permanently to 0. |
pcie0_m_axis_rc_tkeep pcie1_m_axis_rc_tkeep | O | 32 | The assertion of bit i of this bus during a transfer indicates to the
user logic that Dword i of the
pcie(n)_m_axis_rc_tdata bus contains valid data. The core sets this
bit to 1 contiguously for all Dwords starting from the first Dword
of the descriptor to the last Dword of the payload. Thus,
pcie(n)_m_axis_rc_tkeep is set to all 1s in all beats of a packet,
except in the final beat when the total size of the packet is not a
multiple of the width of the data bus (both in Dwords). This is true
for both Dword-aligned and address-aligned modes of payload
transfer. These outputs are permanently set to all 1s when the straddle option is enabled. The user logic must use the signals in pcie(n)_m_axis_rc_tuser in that case to determine the start and end of Completion TLPs transferred over the interface. |
pcie0_m_axis_rc_tvalid pcie1_m_axis_rc_tvalid | O | 1 | The core asserts this output whenever it is driving valid data on the pcie(n)_m_axis_rc_tdata bus. The core keeps the valid signal asserted during the transfer of a packet. The user application can pace the data transfer using the pcie(n)_m_axis_rc_tready signal. |
pcie0_m_axis_rc_tready pcie1_m_axis_rc_tready | I | 1 | Activation of this signal by the user logic
indicates to the PCIe core that the user logic is ready to accept
data. Data is transferred across the interface when both
pcie(n)_m_axis_rc_tvalid and pcie(n)_m_axis_rc_tready are asserted
in the same cycle. If the user logic deasserts the ready signal when the valid signal is High, the core maintains the data on the bus and keep the valid signal asserted until the user logic has asserted the ready signal. |
Bit Index | Name | Width | Description |
---|---|---|---|
127:0 | byte_en | 127 | The client logic may optionally use these byte
enable bits to determine the valid bytes in the payload of a packet
being transferred. The assertion of bit i of this bus during a transfer indicates to the
client that byte i of the
pcie(n)_m_axis_cq_tdata bus contains a valid payload byte. This bit
is not asserted for descriptor bytes. Although the byte enables can be generated by client logic from information in the request descriptor (address and length), the client has the option of using these signals directly instead of generating them from other interface signals. The 1 bits in this bus for the payload of a TLP are always contiguous. |
135:128 | is_sop[7:0] | 8 | Signals the start of a new TLP in this beat.
These outputs are set in the first beat of a TLP. When straddle is
disabled, only is_sop[0] is valid and is_sop[3:1] are permanently
set to 0. When straddle is enabled, the settings are as follows:
Use of this signal is optional for the client when the straddle option is not enabled, because a new TLP always starts in the beat following pcie(n)_m_axis_rc_tlast assertion. |
138:136 | is_sop0_ptr[2:0] | 3 | Indicates the position of the first byte of the
first TLP starting in this beat:
This field is valid only when the straddle option is enabled on the RC interface. Otherwise, it is set to 0 permanently, as a TLP can only start in bye lane 0. |
141:139 | is_sop1_ptr[2:0] | 3 | Indicates the position of the first byte of the second TLP starting in
this beat:
|
144:142 | is_sop2_ptr[2:0] | 3 | Indicates the position of the first byte of the
third TLP starting in this beat:
This output is used only when the straddle option is enabled on the RC interface. The output is permanently set to 0 when straddle is disabled. |
147:145 | is_sop3_ptr[2:0] | 3 | Indicates the position of the first byte of the fourth TLP starting in
this beat:
This output is used only when the straddle option is enabled on the RC interface. The output is permanently set to 0 when straddle is disabled. |
150:148 | is_sop4_ptr[2:0] | 3 | Indicates the position of the first byte of the fifth TLP starting in
this beat:
This output is used only when the straddle option is enabled on the RC interface. The output is permanently set to 0 when straddle is disabled. |
154:151 | is_sop5_ptr[2:0] | Indicates the position of the first byte of the sixth TLP starting in
this beat:
This output is used only when the straddle option is enabled on the RC interface. The output is permanently set to 0 when straddle is disabled. |
|
156:154 | is_sop6_ptr[2:0] | Indicates the position of the first byte of the seventh TLP starting
in this beat:
This output is used only when the straddle option is enabled on the RC interface. The output is permanently set to 0 when straddle is disabled. |
|
159:157 | is_sop7_ptr[2:0] | Indicates the position of the first byte of the eigth TLP starting in
this beat:
This output is used only when the straddle option is enabled on the RC interface. The output is permanently set to 0 when straddle is disabled. |
|
167:160 | is_eop[7:0] | 8 | Signals that one or more TLPs are ending in this
beat only when straddle is enabled. These outputs are set in the
final beat of a TLP. The settings are as follows:
When the straddle option is disabled, pcie(n)_m_axis_rc_tlast indicates the final beat of a TLP. |
172:168 | is_eop0_ptr[4:0] | 5 | Offset of the last Dword of the first TLP ending
in this beat. This output is valid when is_eop[0] is asserted. This output is used only when the straddle option is enabled on the RC interface. The output is permanently set to 0 when straddle is disabled. |
177:173 | is_eop1_ptr[4:0] | 5 | Offset of the last Dword of the second TLP
ending in this beat. This output is valid when is_eop[1] is
asserted. This output is used only when the straddle option is enabled on the RC interface. The output is permanently set to 0 when straddle is disabled. |
182:178 | is_eop2_ptr[4:0] | 5 | Offset of the last Dword of the third TLP ending
in this beat. This output is valid when is_eop[2] is asserted. This output is used only when the straddle option is enabled on the RC interface. The output is permanently set to 0 when straddle is disabled. |
187:183 | is_eop3_ptr43:0] | 5 | Offset of the last Dword of the fourth TLP
ending in this beat. This output is valid when is_eop[3] is
asserted. This output is used only when the straddle option is enabled on the RC interface. The output is permanently set to 0 when straddle is disabled. |
192:188 | is_eop4_ptr[4:0] | 5 | Offset of the last Dword of the fifth TLP ending
in this beat. This output is valid when is_eop[4] is asserted. This output is used only when the straddle option is enabled on the RC interface. The output is permanently set to 0 when straddle is disabled. |
197:193 | is_eop5_ptr[4:0] | 5 | Offset of the last Dword of the sixth TLP ending
in this beat. This output is valid when is_eop[5] is asserted. This output is used only when the straddle option is enabled on the RC interface. The output is permanently set to 0 when straddle is disabled. |
202:198 | is_eop6_ptr[4:0] | 5 | Offset of the last Dword of the seventh TLP
ending in this beat. This output is valid when is_eop[6] is
asserted. This output is used only when the straddle option is enabled on the RC interface. The output is permanently set to 0 when straddle is disabled. |
207:203 | is_eop7_ptr[4:0] | 5 | Offset of the last Dword of the eigth TLP ending
in this beat. This output is valid when is_eop[7] is asserted. This output is used only when the straddle option is enabled on the RC interface. The output is permanently set to 0 when straddle is disabled. |
208 | discontinue | 1 | This signal is asserted by the core in the last
beat of a TLP, if it has detected an uncorrectable error while
reading the TLP payload from its internal FIFO memory. The client
application must discard the entire TLP when such an error is
signaled by the core. This signal is never asserted when the TLP has no payload. It is asserted only in the last beat of the payload transfer, that is when is_eop[0] is High. When the straddle option is enabled, the core does not start a new TLP if it has asserted discontinue in a beat. When the core is configured as an Endpoint, the error is also reported by the core to the Root Complex it is attached to, using Advanced Error Reporting (AER). |
336:209 | parity | 128 | Odd parity for the 1024-bit transmit data. Bit i provides the odd parity computed for byte i of pcie(n)_m_axis_cq_tdata. |