- You must generate a clock for the PS-VIP model. In the hardware, this is
typically an internal clock derived from the on-board PS clock inputs. In
simulation, this clock is modeled for all the internal PS interfaces and it can run
with any frequency ranging from 100 MHz – 1GHz. In the provided examples, you run it
at 1 GHz to match the speed of the CPM PS interconnect of a -2 MHP devices.
This PS-VIP reference clock is provided at the following pin:
versal_cips_0.inst.pspmc_0.inst.PS9_VIP_inst.inst.versal_cips_ps_vip_clk; - You must generate CPM reference clocks. CPM clock operates at 33.33 MHz
matching in the hardware. This is done by calling the following PS9 API:
versal_cips_0.inst.pspmc_0.inst.PS9_VIP_inst.inst.cpm_gen_clock(33.33); - You must generate clocks for the PS PMC model to load your configuration
files. In the hardware, this frequency is up to 200 MHz. In simulation, to speed-up
the configuration file load which can take hours, you can increase to 500 MHz or 1
GHz temporarily. This is done by calling the following PS9 API:
versal_cips_0.inst.pspmc_0.inst.PS9_VIP_inst.inst.cpm_osc_clk_div2_gen_clock(200); - If your design uses PL_CLK pins out of the CIPS IP, you must generate those clocks
by calling the following PS9 API (shown below to generate four PL_CLKs):
versal_cips_0.inst.pspmc_0.inst.PS9_VIP_inst.inst.pl_gen_clock(0,250); versal_cips_0.inst.pspmc_0.inst.PS9_VIP_inst.inst.pl_gen_clock(1,250); versal_cips_0.inst.pspmc_0.inst.PS9_VIP_inst.inst.pl_gen_clock(2,250); versal_cips_0.inst.pspmc_0.inst.PS9_VIP_inst.inst.pl_gen_clock(3,250);