Introduction to the CPM4 - 3.4 English

Versal Adaptive SoC CPM Mode for PCI Express Product Guide (PG346)

Document ID
PG346
Release Date
2024-05-30
Version
3.4 English

The integrated block for PCIe® Rev. 4.0 with DMA and CCIX Rev. 1.0 (CPM4) consists of two PCIe® controllers, DMA features, CCIX features, and network on chip (NoC) integration. The Versal Adaptive SoC CPM Mode for PCI Express enables direct access to the two high-performance, independently customizable PCIe controllers. The CPM4 uses up to 16 Versal device GTY channels over the XPIPE. Application designs can also interface to the CPM4 with soft logic and clocking resources in the programmable logic. All feature references are applicable to both instances of CPM4 PCIe controllers, with the following exceptions:

  • CPM4 PCIe Controller 0 supports up to x16 operation, and CPM4 PCIe Controller 1 supports up to x8 operation.
  • CPM4 PCIe Controller 1 with up to x8 support is available only when CPM4 PCIe Controller 0 is configured with 8 lanes or fewer.
  • The CPM4 DMA features are supported only with CPM4 PCIe Controller 0. For more information about CPM4 DMA features, see the Versal Adaptive SoC CPM DMA and Bridge Mode for PCI Express Product Guide (PG347).
Figure 1. CPM4 Sub-Block for PCIe Function (CPM4 PCIE)

The CPM4 PCIe controllers are designed as per the PCI Express Base Specification Revision 4.0 and support the Gen4 data rate (16 GT/s per lane). They also support the Gen1 (2.5 GT/s per lane), Gen2 (5 GT/s per lane), and Gen3 (8 GT/s per lane) data rates. They can interoperate with components that are compliant with all versions of the PCI Express Base Specification.

The CPM4 PCIe controllers are available through the Vivado IP catalog in the Vivado Integrated Design Environment (IDE). The combination of the CPM4 PCIe controllers, the GTY, and clocking implement all layers of the PCI Express protocol, and the configuration space and controller.