Completer Completion Descriptor Format - 3.4 English

Versal Adaptive SoC CPM Mode for PCI Express Product Guide (PG346)

Document ID
PG346
Release Date
2024-05-30
Version
3.4 English

The user application sends completion data for a completer request to the completer completion interface of the core as an independent AXI4-Stream packet. Each packet starts with a descriptor, and can have payload data following the descriptor. The descriptor is always 12 bytes long, and is sent in the first 12 bytes of the completion packet. The descriptor is always transferred in the first beat of a Completion TLP. When the user application splits the completion data for a request into multiple Split Completions, it must send each Split Completion as a separate AXI4-Stream packet, with its own descriptor.

The format of the completer completion descriptor is illustrated in the following figure. The individual fields of the completer request descriptor are described in the following table.

Figure 1. Completer Completion Descriptor Format
Table 1. Completer Completion Descriptor Fields
Bit Index Field Name Description
6:0 Lower Address For memory read Completions, this field must be set to the least significant 7 bits of the starting byte-level address of the memory block being transferred. For the first (or only) Completion, the Completer can generate this field from the least significant 5 bits of the address of the Request concatenated with 2 bits of byte-level address formed by the byte enables for the first Dword of the Request as shown below.
first_be[3:0] Lower Address[1:0]
4'b0000 2'b00
4'bxxx1 2'b00
4'bxx10 2'b01
4'bx100 2'b10
4'b1000 2'b11

For any subsequent Completions, the Lower Address field is always zero except for Completions generated by a Root Complex with a Read Completion Boundary (RCB) value of 64 bytes. In this case the least significant 6 bits of the Lower Address field is always zero and the most significant bit of the Lower Address field toggles according to the alignment of the 64-byte data payload.

For all other Completions, the Lower Address must be set to all zeros.

7 Reserved This bit is reserved.
9:8 Address Type This field is defined for Completions of memory transactions and Atomic Operations only. For these Completions, the user logic must copy the AT bits from the corresponding request descriptor into this field. This field must be set to 0 for all other Completions.
15:10 Reserved This bit is reserved.
28:16 Byte Count

These 13 bits can have values in the range of 0 – 4,096 bytes. If a Memory Read Request is completed using a single Completion, the Byte Count value indicates Payload size in bytes. This field must be set to 4 for I/O read Completions and I/O write Completions. The byte count must be set to 1 while sending a Completion for a zero-length memory read, and a dummy payload of 1 Dword must follow the descriptor.

For each Memory Read Completion, the Byte Count field must indicate the remaining number of bytes required to complete the Request, including the number of bytes returned with the Completion.

If a Memory Read Request is completed using multiple Completions, the Byte Count value for each successive Completion is the value indicated by the preceding Completion minus the number of bytes returned with the preceding Completion. The total number of bytes required to complete a Memory Read Request is calculated as shown in the following table.

MSB of the Byte Count field is reserved.

29 Locked Read Completion This bit must be set when the Completion is in response to a Locked Read request. It must be set to 0 for all other Completions.
30 Reserved This bit is reserved.
31 T8 When 10b Tag Completer is enabled, this bit is to carry PCIe Tag[8]. This bit is reserved in all other cases.
42:32 Dword Count These 11 bits indicate the size of the payload of the current packet in Dwords. Its range is 0 - 1K Dwords. This field must be set to 1 for I/O read Completions and 0 for I/O write Completions. The Dword count must be set to 1 while sending a Completion for a zero-length memory read. The Dword count must be set to 0 when sending a UR or CA Completion. In all other cases, the Dword count must correspond to the actual number of Dwords in the payload of the current packet.
45:43 Completion Status

These bits must be set based on the type of Completion being sent. The only valid settings are:

  • 000: Successful Completion
  • 001: Unsupported Request (UR)
  • 100: Completer Abort (CA)
46 Poisoned Completion This bit can be used to poison the Completion TLP being sent. This bit must be set to 0 for all Completions, except when the user application detects an error in the block of data following the descriptor and wants to communicate this information using the Data Poisoning feature of PCI Express.
47 T9 When 10b Tag Completer is enabled, this bit is to carry PCIe Tag[9]. This bit is reserved in all other cases.
63:48 Requester ID PCI Requester ID associated with the request (copied from the request).
71:64 Tag PCI Express Tag associated with the request (copied from the request).
79:72

Target Function/

Device Number

Device and/or Function number of the Completer Function.

Endpoint mode:

ARI enabled:

  • Bits [79:72] must be set to the Completer Function number.

ARI disabled:

  • Bits [74:72] must be set to the Completer Function number.
  • Bits [79:75] are not used

Upstream Port for Switch use case (Endpoint mode is selected within the IP):

ARI enabled:

  • Bits [79:72] must be set to the Completer Function number.

ARI disabled:

  • Bits [74:72] must be set to the Completer Function number.
  • Bits [79:75] are not used if the Completion is originating from the switch itself. These bits must be set to the Completer Device number where the Completion was originated if the switch is relaying the Completion (Completer is external to the switch). This is used with Completer ID Enable bit in the descriptor.

Root Port mode (Downstream Port):

ARI enabled:

  • Bits [79:72] must be set to the Completer Function number.

ARI disabled:

  • Bits [74:72] must be set to the Completer Function number.
  • Bits [79:75] must be set to the Completer Device number. This is used in conjunction with Completer ID Enable bit in the descriptor.
87:80 Completer Bus Number Bus number associated with the Completer Function.
Endpoint mode:
  • Not Used

Upstream Port for Switch use case (Endpoint mode is selected within the IP):

  • Not used if the Completion is originating from the switch itself. These bits must be set to the Completer Bus number where the Completion was originated if the switch is relaying the Completion (Completer is external to the switch). This is used in conjunction with Completer ID Enable bit in the descriptor.

Root Port mode (Downstream Port):

  • Must be set to the Completer Bus number. This is used in conjunction with Completer ID Enable bit in the descriptor.
88 Completer ID Enable Values are:
  • 1'b1: The client supplies Bus, Device, and Function numbers in the descriptor to be populated as the Completer ID field in the TLP header.
  • 1'b0: IP uses Bus and Device numbers captured from received Configuration requests and the client supplies Function numbers in the descriptor to be populated as the Completer ID field in the TLP header.

Endpoint mode:

  • Must be set to 1'b0.

Upstream Port for Switch use case (Endpoint mode is selected within the IP):

  • Set to 1'b0 when the Completion is originating from the switch itself.
  • Set to 1'b1 when the switch is relaying the Completion (Completer is external to the switch). This is used with Completer Bus Number bits [95:88] and Completer Function/Device Number bits [87:83] when ARI is not enabled.

Root Port mode:

  • Must be set to 1'b1. This is used in conjunction with Completer Bus Number bits [95:88] and Completer Function/Device Number bits [87:83] when ARI is not enabled.
91:89 Transaction Class (TC) PCIe Transaction Class (TC) associated with the request. The user application must copy this value from the TC field of the associated request descriptor.
94:92 Attributes PCIe attributes associated with the request (copied from the request). Bit 92 is the No Snoop bit, bit 93 is the Relaxed Ordering bit, and bit 94 is the ID-Based Ordering bit.
95 Force ECRC Force ECRC insertion. Setting this bit to 1 forces the integrated block to append a TLP Digest containing ECRC to the Completion TLP, even when ECRC is not enabled for the Function sending the Completion.