System Bring-Up - 3.4 English

Versal Adaptive SoC CPM Mode for PCI Express Product Guide (PG346)

Document ID
PG346
Release Date
2024-05-30
Version
3.4 English

The first step is to program the FPGA and power on the system such that the PCIe link is detected by the host system. This can be accomplished by either:

  • Programming the design file into the flash present on the FPGA board, or
  • Programming the device directly via JTAG

If the card is powered by the Host PC, it will need to be powered on to perform this programming using JTAG and then restarted to allow the PCIe link to enumerate. After the system is up and running, you can use the Linux lspci utility to list the details for the FPGA-based PCIe device.