Configuration Management Interface - 3.4 English - PG346

Versal Adaptive SoC CPM Mode for PCI Express Product Guide (PG346)
Document ID
PG346
Release Date
2024-11-22
Version
3.4 English

The configuration management interface is used to read and write to the configuration space registers. The following table defines the ports in the configuration management interface of the core.

Note: The pcie0* signals map to PCIe Controller 0 and pcie1* signals map to PCIe Controller 1 in the port descriptions below.
Table 1. Configuration Management Interface Port Descriptions
Port I/O Width Description
pcie0_cfg_mgmt_addr pcie1_cfg_mgmt_addr I 10 Read/Write Address

Configuration Space Dword-aligned address.
pcie0_cfg_mgmt_function_number pcie1_cfg_mgmt_function_number I

8 for CPM4

16 for CPM5

 Selects the PCI function number for the configuration register read/write.
pcie0_cfg_mgmt_write pcie1_cfg_mgmt_write I 1 Write Enable

Asserted for a write operation. active-High.
pcie0_cfg_mgmt_write_data pcie1_cfg_mgmt_write_data I 32 Write data

Write data is used to configure the Configuration and Management registers.
pcie0_cfg_mgmt_byte_enable pcie1_cfg_mgmt_byte_enable I 4 Byte Enable

Byte enable for write data, where pcie(n)_cfg_mgmt_byte_enable[0] corresponds to pcie(n)_cfg_mgmt_write_data[7:0], and so on.
pcie0_cfg_mgmt_read pcie1_cfg_mgmt_read I 1 Read Enable

Asserted for a read operation. Active-High.
pcie0_cfg_mgmt_read_data pcie1_cfg_mgmt_read_data O 32 Read data out

Read data provides the configuration of the Configuration and Management registers.
pcie0_cfg_mgmt_read_write_done pcie1_cfg_mgmt_read_write_done O 1 Read/Write operation complete

Asserted for 1 cycle when operation is complete. Active-High.
pcie0_cfg_mgmt_debug_access pcie1_cfg_mgmt_debug_access I 1 Type 1 RO, Write

When the core is configured in the Root Port mode, asserting this input during a write to a Type-1 configuration space register forces a write into certain read-only fields of the register (see description of RC-mode Config registers). This input has no effect when the core is in the Endpoint mode, or when writing to any register other than a Type-1 configuration space register.