Enabling PCIe Link Debug - 3.4 English

Versal Adaptive SoC CPM Mode for PCI Express Product Guide (PG346)

Document ID
PG346
Release Date
2024-05-30
Version
3.4 English

Use this guide to enable and connect PCIe link debug in a Vivado IP integrator design. This section only describes the additional connections that should be added to enable PCIe link debug in a design. It does not discuss how to properly connect the PCIe enabled IPs to create a working design. Block automation can be used, or the connectivity and connections described below should be added to an existing design and IP configuration.

  1. Enable this option in the core customization wizard, and select the options in the customization GUI, as shown below. The CPM PCIE cores are customized through the CIPS IP and for PL PCIE cores are customized through the AMD Versal adaptive SoC Integrated Block for PCIe IP.

    This adds the PCIe debug core to the PCIe IP and exposes the debug AXI4-Stream interfaces and ports. The debug AXI4-Stream and interface ports should be connected to a debug hub IP within an AMD Versal adaptive SoC design to enable debug for the design. The PCIe example design provides one implementation of how the Debug Hub IP can be connected in an AMD Versal adaptive SoC designs. This is also detailed in the description below.

  2. Add the debug hub IP to the design and use the following configuration options to enable the Debug Hub AXI4 interface along with one set of AXI4-Stream interfaces. Additional AXI4-Stream interfaces can be enabled and connected in your design as desired.

  3. Add the CIPS IP to the design or configure the existing CIPS IP and include the following configuration options. These options enable an AXI Master, clock, and reset that can be connected to the debug hub IP. To do so:
    1. Select PS-PMC > Clock Configuration > Output Clocks > PMC Domain Clocks > PL Fabric Clocks selection enable a 100 MHz or similar output clock.

    2. Select PS-PMC > PL-PS Interfaces, and enable at least one PL reset in Number of PL Resets, and the M_AXI_LPD AXI master.

  4. Add and configure the Processor System Reset IP.

  5. Connect the IPs as shown in the following figures. This can be customized to fit with the existing design connectivity.

After the debug connections are added to an Vivado IP integrator design, as shown above, PCIe link debug is enabled in the generated .pdi image. The connections shown above should be added to a full design and are not sufficient to create a working design alone. The PCIe IP ports and the remainder of the design must be created and configured as per the desired operation of the PCIe enabled IP.