Enabling PCIe Link Debug - Enabling PCIe Link Debug - 3.4 English - PG346

1. Enable this option in the core customization wizard, and select the options in the customization GUI, as shown below. Customize the CPM PCIe cores through the CIPS IP and the PL PCIe cores through the AMD Versal Adaptive SoC Integrated Block for PCIe IP.
   
   

   This adds the PCIe debug core to the PCIe IP and exposes the debug AXI4-Stream interfaces and ports. The debug AXI4-Stream and interface ports must be connected to a debug hub IP within an AMD Versal adaptive SoC design to enable debug for the design. The PCIe example design provides an implementation that shows how to connect the Debug Hub IP in AMD Versal adaptive SoC designs. This is also detailed in the following description.

2. Add the debug hub IP to the design and use the following configuration options to enable the Debug Hub AXI4 interface along with one set of AXI4-Stream interfaces. You can enable and connect additional AXI4‑Stream interfaces in your design as required.
   
   
3. Add the CIPS IP to the design or configure the existing CIPS IP and include the following configuration options. These options enable an AXI Master, clock, and reset that can be connected to the debug hub IP. To do so:
   1. Select PS-PMC > Clocking > Output Clocks > PMC Domain Clocks > PL Fabric Clocks selection enable a 100 MHz or similar output clock.
      
      
   2. Select PS-PMC > PL-PS Interfaces, and enable at least one PL reset in Number of PL Resets, and the M_AXI_LPD AXI master.
      
      
4. Add and configure the Processor System Reset IP.
   
   
5. Connect the IPs as shown in the following figures. You can customize this to fit the existing design connectivity.
   
   

After the debug connections are added to a Vivado IP integrator design, as shown above, the generated .pdi image enables PCIe link debug. The connections shown above are added to a full design and are not sufficient to create a working design on their own. The PCIe IP ports and the remainder of the design are created and configured according to the required operation of the PCIe‑enabled IP.