Connecting to PCIe Link Debug in Vivado - 3.4 English

Versal Adaptive SoC CPM Mode for PCI Express Product Guide (PG346)

Document ID
PG346
Release Date
2024-05-30
Version
3.4 English
Use the following steps to connect Vivado Hardware Manager to the FPGA and associated PCIe link debug enabled design.
  1. Open the Hardware Manager.
  2. Select the device from the Tools > Program Device… drop-down menu.
  3. Select the .pdi and .ltx files for programming the device, and select Program.
    Note: You should not load the .ltx file and refresh the target until after the .pdi file has been programmed.


  4. Select the PCIe Debug core in the Hardware window. You see three main views that include the PCIe Debug Core Properties, PCIe Link LTSSM State Trace, and the PCIe Link LTSSM State Diagram with transitions.

Using this view, you can observe the active PCIe link status and state transitions. In the PCIe Debug Core Properties window, you can see the name of the PCIe debug core (PCIe_0), the current link status (Gen3x8), and the connected GTs (Quads 103 and 104). The PCIe LTSSM State Trace view shows a hierarchical view of the PCIe LTSSM state machine transitions. The PCIe LTSSM State Diagram provides a graphical display of the PCIe LTSSM states transitions that were traversed during the PCIe link up process. Visited LTSSM states are shown in green, the final or current LTSSM state is shown in yellow and the number of times each transition was traversed is identified on the arcs between states.

In addition to the graphical display, the report_hw_pcie command can be used to generate a console text report that contains the PCIe debug information. This information can be shared with others to aid in debugging PCIe Link issues. For this example, the name of the debug core is PCIe_0, and is inserted into the command.

report_hw_pcie PCIe_0

This information helps determine where in the PCIe link-up process an issue occurred and can guide further debug of link related issues.