Versal Adaptive SoC CPM Mode for PCI Express Product Guide (PG346) - 3.4 English

Document ID: PG346
Release Date: 2024-11-22
Version: 3.4 English

Overview
Navigating Content by Design Process
Introduction to the CPM4
Protocol Layers
AXI4-Stream Layer
Transaction Layer
CCIX Transaction Layer
Data Link Layer
Physical Layer
Standards
Features
Introduction to the CPM5
Protocol Layers
AXI4-Stream Layer
Transaction Layer
CCIX Transaction Layer
Data Link Layer
Physical Layer
Standards
Features
Use Modes
PCI Express Endpoint Use Modes
PCI Express Root Port Use Mode
PCI Express Switch Port Use Mode
Unsupported Features
Licensing and Ordering
Tandem Configuration
Overview
Supported Devices
Tandem + DFX
Enable the Tandem Configuration Solution
Deliver Programming Images to Silicon
Tandem Configuration Performance
Design Operation
Loading Tandem PCIe for Stage 2
Design Requirements
Using the Provided Software and Drivers
QDMA
XDMA (CPM4 Only)
MCAP VSEC
Design Version Compatibility Checks
Tandem PCIe and DFX Configuration Example Design
Segmented Configuration
Known Issues and Limitations
Product Specification
Minimum Device Requirements
Port Descriptions
AXI4-Stream Core Interfaces
64/128/256-Bit Interfaces
Completer Request Interface
Completer Completion Interface
Requester Request Interface
Requester Completion Interface
512-bit Interfaces
Completer Request Interface
Completer Completion Interface
Requester Request Interface
Requester Completion Interface
1024-bit Interfaces
Completer Request Interface
Completer Completion Interface
Requester Request Interface
Requester Completion Interface
Clock and Reset Interface
Configuration Management Interface
Configuration Status Interface
Configuration Received Message Interface
Configuration Transmit Message Interface
Configuration Flow Control Interface
Transmit Flow Control Interface
Configuration Control Interface
Configuration Interrupt Controller Interface
Legacy Interrupt Interface
MSI Interrupt Interface
MSI-X Interrupt Interface
Configuration Extend Interface
Configuration VC1 Status Interface
Configuration PASID Interface
Configuration Space
Designing with the Core
Clocking
Resets
AXI4-Stream Interface Description
1024-Bit Completer Interface
Completer Request Interface Operation (1024-bits)
Completer Request Descriptor Formats
Completer Memory Write Operation
Completer Memory Read Operation
Aborting a Transfer
Selective Flow Control for Non-Posted Requests
Straddle Option on CQ Interface
Completer Completion Interface Operation (1024-bits)
Completer Completion Descriptor Format
Completions with Successful Completion (SC) Status
Aborting a Completion Transfer
Completions with Error Status (UR and CA)
Straddle Option on CC Interface
1024-Bit Requester Interface
Requester Request Interface Operation (1024-bits)
Requester Request Descriptor Formats
Requester Memory Write Operation
Non-Posted Transactions with No Payload
Non-Posted Transactions with a Payload
Aborting a Transfer
Straddle Option on RQ Interface
Tag Management for Non-Posted Transactions
Avoiding Head-of-Line Blocking for Posted Requests
Maintaining Transaction Order
Requester Completion Interface Operation (1024-bits)
Requester Completion Descriptor Format
Transfer of Completions with No Data
Transfer of Completions with Data
Straddle Option for RC Interface
Aborting a Completion Transfer
Handling of Completion Errors
Link Training: 2-Lane, 4-Lane, 8-Lane, and 16- Lane Components
Link Partner Supports Fewer Lanes
Lane Becomes Faulty
Lane Reversal
Design Flow Steps
Customizing and Generating the CIPS IP Core for CPM4
Configuring the CIPS IP Core
Basic Mode Parameters
Basic Tab
Capabilities Tab
PF IDs Tab
PF BARs Tab
Legacy/MSI Cap Tab
Advanced Mode Parameters
Basic Tab
Capabilities Tab
MSI-X Capabilities Tab
SRIOV Config Tab
SRIOV VF BARs Tab
Adv. Options
Interface Parameters
Customizing and Generating the CIPS IP Core for CPM5
Configuring the CIPS IP Core
Basic Mode Parameters
Basic Tab
Capabilities Tab
PF IDs Tab
PF BARs Tab
Legacy/MSI Cap Tab
Advanced Mode Parameters
Basic Tab
Capabilities Tab
MSI-X Capabilities Tab
SRIOV Config Tab
SRIOV PF BARs Tab
Adv. Options-1
Interface Parameters
MCAP Register Description
MCAP PCI Express Extended Capability Header Register (0x00, RO)
MCAP Vendor Specific Header Register (0x04, RO)
MCAP Status Register (0x08, RW)
MCAP Control Register (0x0C, RW)
MCAP Read/Write Address Register (0x10, RW)
MCAP Write Data Register (0x14, WO)
MCAP Read Data Register (0x18, RO)
GT Selection and Pin Planning for CPM4
CPM4 GT Selection
CPM4 Additional Considerations
CPM4 GTY Locations
GT Quad Locations
GT Selection and Pin Planning for CPM5
General Guidance for CPM5
GTYP Quad and REFCLK Placements
RESET Placements
CPM5 Configuration Notes
Guidance for CPM5 in Specifically Identified Engineering Sample Devices
GTYP Quad and REFCLK Placements
RESET Placements
CPM5 Configuration Notes
Guidance for CPM5 Migration from Specifically Identified Engineering Sample Devices
GTYP Quad and REFCLK Considerations
RESET Considerations
CPM5 Configuration Considerations
CPM5 GTYP Locations
Generating Simulation Example Design for CPM
Introduction
Limitations
Example Package
CPM5 PCIe BMD
CPM5 QDMA MM
Preparation and Setup
Preparing Design
Preparing the Test Bench
Preparing Simulation
Required Minimum PS9 API
Clocks
Resets
Data Routing
CDO Selection
Supported PS9 API
CPM Customizable Example Design
Designs
Available Designs
CPM4 Designs
Versal_CPM_PCIE_PIO_EP_Design
Versal_CPM_PCIE_BMD_EP_Design
Versal_CPM_PCIE_BMD_EP_Simulation_Design
Versal_CPM_Tandem_PCIe_DFX
Versal_CPM_Bridge_RP_Design
CPM5 Designs
Versal_CPM_PCIE_PIO_EP_Design
Versal_CPM_PCIE_BMD_EP_Design
Versal_CPM_PCIE_BMD_EP_Simulation_Design
Versal_CPM_Tandem_PCIe_DFX
Versal_CPM_Bridge_RP_Design
Versal_CPM5_Two_Port_Switch_Design
CED Generation Steps
Simulation CED Generation Steps
Managing Receive-Buffer Space for Inbound Completions
General Considerations and Concepts
Completion Space
Maximum Request Size
Read Completion Boundary
Important Note For High Performance Applications
Methods of Managing Completion Space
LIMIT_FC Method
PACKET_FC Method
RCB_FC Method
DATA_FC Method
Debugging
Finding Help with AMD Adaptive Computing Solutions
Documentation
Debug Guide
Answer Records
Master Answer Record for the Core
Technical Support
PCIe Link Debug Enablement
Enabling PCIe Link Debug
Connecting to PCIe Link Debug in Vivado
Using the High Speed Debug Port Over PCIe for Design Debug
Overview
Host PC HSDP-PCIe Driver
Host PC hw_server Application
HSDP-over-PCIe Enabled FPGA Design
User Mode
Management Mode
Implementing the HSDP-over-PCIe Example Design
Opening the Example Design and Generating a Bitstream
System Bring-Up
Compiling and Loading the Driver
Launch hw_server on the Remote or Local Host PC
Connecting the Vivado IDE to the hw_server Application for Debug Over PCIe
Interrupt Request (IRQ) Routing and Programming for CPM4
Interrupt Request (IRQ) Routing and Programming for CPM5
Limitations for CPM4 and CPM5
Migrating
Migrating to CPM4
Ports
GT Locations
Clocking
Reset
Features
New Features
Features Not Available, or Limited Usage Features
Attributes
Migrating to CPM5
Ports
GT Locations
Clocking
Reset
Features
New Features
Features Not Available, or Limited Usage Features
Attributes
Additional Resources and Legal Notices
Finding Additional Documentation
Support Resources
References
Revision History
Please Read: Important Legal Notices

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