Clocking - 3.4 English

Versal Adaptive SoC CPM Mode for PCI Express Product Guide (PG346)

Document ID
PG346
Release Date
2024-05-30
Version
3.4 English

CPM5 requires the same reference clock as UltraScale+ devices on the input side. On the output side, only pcie(n)_user_clk is available for the fabric (user logic). The pcie(n)_user_clk signal can have a frequency of 62.5, 125, or 250 MHz depending on the configured link speed and width.