Design Operation - 3.4 English

Versal Adaptive SoC CPM Mode for PCI Express Product Guide (PG346)

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3.4 English

Though the CPM is a hardened integrated block, many features and options that can be selected during CIPS configuration require implementation in the programmable soft logic (PL). Any part of the design that has been implemented in the PL is configured in stage 2. Design configurations that require PL resources during PCIe enumeration should not be used with Tandem PROM or Tandem PCIe. Specifically, the PCIe extended capability interface should not be enabled for Tandem modes because these registers are addressed during enumeration and these are not present in the stage 1 portion of the design. Moreover, any other resource in the Versal device, such as the R5 or A72 processors in the Scalar Engines are programmed after the CPM and its PCI Express endpoint(s). While future enhancements to the Tandem Configuration solution might open opportunities to quickly booting other dedicated parts of a target device, the current solution focuses exclusively on PCI Express end points in the CPM only for the sole purpose of meeting the 100 ms boot time requirement.