Resets - 3.4 English

Versal Adaptive SoC CPM Mode for PCI Express Product Guide (PG346)

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3.4 English
  • You must generate POR reset to the chip by calling the following PS9 API. This reset is required to be released for CDO load to start.
    #wait 500ns
  • You must generate PCIe reset to each PCIe controllers enabled (PERST0N and PERST1N). If not used, user can hold its reset pin asserted. This reset must be held asserted until CDO load is complete. You get an indication in the simulation log when CDO load has finished.
    versal_cips_0.inst.pspmc_0.inst.PS9_VIP_inst.inst.PERST0N = 1'b0;
    versal_cips_0.inst.pspmc_0.inst.PS9_VIP_inst.inst.PERST1N = 1'b0;
    #wait for CDO load to complete
    versal_cips_0.inst.pspmc_0.inst.PS9_VIP_inst.inst.PERST0N = 1'b1;
    versal_cips_0.inst.pspmc_0.inst.PS9_VIP_inst.inst.PERST1N = 1'b1;
  • If your design uses PL_RST pins out of the CIPS IP, you must generate those resets by calling the following PS9 API (shown below to generate four PL_RSTs). PL reset can be held as long or as short as user desire. It must be released after POR has been released and PL clock has been started, but no dependencies to the PERSTs reset.
    #wait user defined length