The AXI4-Stream layer implements AMD specific requirements. In the transmit or outbound direction, the AXI4 layer interfaces the transaction layer with two AXI4-Stream interfaces. In the receive or inbound direction, the transaction layer output is forwarded to two AXI4-Stream interfaces. Application designs can attach to the AXI4-Stream interfaces, exchange information with the Versal Adaptive SoC CPM Mode for PCI Express encoded as an AMD specific streaming protocol implementation, and run on top of the industry standard AXI4-Stream interface. The CPM4 PCIe controllers support management of up to 256 (extended tag) or 768 (10 bit Tag) outstanding customer initiated read requests, as part of the streaming protocol. The AXI4-Stream layer supports:
- Reception and transmission of address translation services (ATS) invalid requests, ATS invalid completions, ATS page requests and ATS PRG response message TLPs, which enable ATS to be implemented in the fabric logic.
- AXI4-Stream interface widths of 64 bits, 128 bits, 256 bits, 512 bits, and 1024 bits.