HSDP-over-PCIe Enabled FPGA Design - 3.4 English

Versal Adaptive SoC CPM Mode for PCI Express Product Guide (PG346)

Document ID
PG346
Release Date
2024-05-30
Version
3.4 English

Traditionally, hardware debug through AMD Vivado is performed over a JTAG interface. For Versal device, the JTAG datapath to the DPC is hardened and abstracted away using Vivado IDE. Making debug seamless requires that the connections are established among the debug target(s), DPC, and debug target clock(s) are active and reset(s) are deasserted. To enable the HSDP-over-PCIe feature on a Versal device, there are several design requirements that must be met. As mentioned previously, there are two distinct methods to exercise the HSDP-over-PCIe feature such as mgmt mode and user mode. Each of these methods has its own design requirements and supporting driver code.