This appendix includes guidance on Interrupt Request (IRQ) pins routing and programming for CPM5. AMD Versal Adaptive SoC CPM Mode for PCIe provides three independent IRQ pins routed to the Programmable Logic (PL) region as well as three independent IRQ pins routed to the hardened Processing System (PS) region. These IRQ pins are shared between the two PCIe controllers and all CPM5 use modes and can be programmed by user to route one or many Interrupt sources.
The three IRQ pins routed to the PL region are named
cpm_misc_irq, cpm_cor_irq, and
cpm_uncor_irq and these signals are visible in the Vivado block diagram canvas on the AMD
Versal CIPS IP boundary. Although, the IRQ pins are named after
miscellaneous, correctable, and uncorrectable respectively, they function identically
from each other and have the same list of interrupt source to select from. Therefore,
you can assume these IRQ pins as three separate general purpose IRQ pins.
The three IRQ pins routed to the PS regions are named similarly. However, they are not visible in the Vivado block diagram canvas and they are using hardened silicon routing. These paths are always enabled and no extra customization is required during CIPS IP customization to use it. These IRQ pins also function identically and have the same list of Interrupt source to select from as the PL IRQ pins counterparts and can be used with the PL IRQ pins.
There are many Interrupt source to select from and the complete list is available in the Versal Adaptive SoC Register Reference (AM012). This appendix provides one use case example to showcase how the IRQ pins mux registers are programmed and includes firmware guidance to service the Interrupt Request.
Example: Generate Interrupt Request for PCIe Reset Event
In this example, generate interrupt whenever PCIe reset (PERST)
is received for PCIe0 and PCIe1 controller. You route
the interrupt generated from PCIe0 controller to the PS region while
interrupt generated from PCIe1 controller to the PL region. You use
the cpm_misc_irq pin as an example, but any other pins can also be
used. A high level block diagram of the interrupt routing is shown in the following
diagram:
- Register programming to enable PCIe reset (PERST) event interrupt
- The following register is programmed at runtime to enable the interrupt:
- Interrupt service routine
- The following steps outline the recommended procedure to service the interrupt request: