CPM4 Additional Considerations - 3.4 English

Versal Adaptive SoC CPM Mode for PCI Express Product Guide (PG346)

Document ID
PG346
Release Date
2024-05-30
Version
3.4 English

To facilitate migration from AMD UltraScale™ or AMD UltraScale+™ designs, boards might be designed to use either CPM4 or PL PCIE integrated blocks to implement PCIe solutions. When designing a board to use either CPM4 or the PL PCIE hardblock, the CPM4 pin selection and planning guidelines should be followed because they are more restrictive. By doing this a board can be designed that works for either a CPM4 or PL PCIE implementation. To route the PCIe reset from the CPM4 to the PL for use with a PL PCIE implementation, the following option needs to be enabled under PS-PMC in the CIPS IP customization GUI.

Figure 1. Configuring the PS PMC

When this option is enabled the PCIe reset for each disabled CPM4 PCIE controller is routed to the PL. The same CPM4 pin selection limitations apply and the additional PCIe reset output pins are exposed at the boundary of the CIPS IP. If the CPM4 PCIE controller is enabled, the PCIe reset is used internal to the CPM4 and is not routed to the PL for connectivity to PL PCIE controllers.