- CPM5 EP simulation requires Versal adaptive SoC
H10 RP as the link partner (can be either CPM5 or PL PCIE5), and vice versa.
Simulation models based on earlier silicon might not work due to the discrepancies
on how the GTs are modeled. Simulation models are typically set to do "speed-up"
during speed changes by shortening the Ordered sets and Timeout values. These values
used are much shorter than PCIe specification calls
for but is beneficial in shortening simulation times.Note: CPM4 is seen to work with UltraScale+ simulation model. However, CPM4 to PL PCIE4 simulation is also preferred.
- Simulation time is longer compared to PL-based IPs. CPM5 simulation is expected to run for about 1-2 hours of wall time. CPM4 simulation is expected around one hour of wall time to complete CPM programming, reset, PCIe link up procedure, and basic data transfers across the PCIe link.
- Certain modules are bypassed or modeled slightly differently from the
hardware behavior. For example, CPM5 DPLL is not used to generate the PL clock,
rather a passthrough clock is used. The use of BFM for PS9 and interconnects.
Therefore, these models might have slightly different characteristics (latencies)
than hardware. Although, the functionality is maintained as accurate as possible,
such as the data pipe width, data routing, interface handshake and so on.Note: CPM4 can have its modules modeled slightly differently than CPM5 even when they share the same name.
- For QDMA/Bridge mode simulation, PCIe reset after initial first link up, link down, Secondary Bus Reset (all activity that causes PCIe link re-train apart from the first link up activity), cannot be simulated. This is due to the required CDO re-programming when DMA reset occurs. PCIe controller mode simulation is not affected by this limitation.