Configuration Space - 3.4 English

Versal Adaptive SoC CPM Mode for PCI Express Product Guide (PG346)

Document ID
PG346
Release Date
2024-05-30
Version
3.4 English

The configuration space is a register space defined by each revision of the PCI Express Base Specification (https://www.pcisig.com/specifications). CPM4 conforms to the PCI Express Base Specification 4.0 and CPM5 conforms to the PCI Express Base Specification 5.0. The Versal Adaptive SoC CPM Mode for PCIe supports AMD proprietary read/write configuration interfaces into this register space, CPM4 supports up to four Physical Functions (PFs) and 252 Virtual Functions (VFs). CPM5 supports up to 16 Physical Functions (PFs) and 4080 Virtual Functions (VFs).

The PCI configuration space consists of the following primary parts.

Legacy PCI Type 0/1 Configuration Space Header

  • Type 0 Configuration Space Header supported for Endpoint configuration
  • Type 1 Configuration Space Header supported for Root, Switch Port configuration

Configuration Space Capabilities

  • PCIe capability
  • Power management capability
  • Message signaled interrupt (MSI) capability
  • MSI-X capability
  • Legacy Extend capabilities
Table 1. CPM4 and CPM5 PCI Configuration Space Capabilities Base Address as Endpoint
Capability PF VF RP/Switch Presence
PCI Power Management 0x40 - Y
MSI 0x48 - Y
MSI-X 0x60 0x60 -
PCI Express 0x70 0x70 Y
Configuration Extend Interface 0xB0 - -

CPM4/CPM5 PCIe Extended Configuration Space Capabilities

  • Advanced Error Reporting Capability
  • Function Level Reset
  • ASPM L1 Support (ASPM support for endpoint port types only; ASPM is not supported for other port types).
  • ASPM L0s Support (ASPM support for endpoint port types only; ASPM is not supported for other port types. Supported in Gen1 and Gen2 configurations only).
  • Device Serial Number Capability
  • Virtual Channel Capability
  • ARI Capability (optional)
  • SR-IOV Extended Capability Structure
  • Configuration Space Extend Capabilities
  • Address Translation Services (ATS)
  • Page Request Interface (PRI)
  • Feature DLLP
  • CCIX Transport DVSEC through configuration space extension
  • CCIX Protocol DVSEC through configuration space extension
  • Transaction Tag Scaling as Requester and Completer
  • Flow Control Scaling
  • MCAP Interface for Staged Configuration and Dynamic Function eXchange per PCI Express port
  • PASID Capability
  • Lane Margining at the Receiver Capability
  • Physical Layer 16 GT/s Capability
  • Physical Layer 32GT/s Capability for CPM5 only
Table 2. CPM4 PCIe Extended Configuration Space Capabilities Base Address as Endpoint
Extended Capability PF 1 VF RP/Switch Presence
Advanced Error Reporting 0x100 - Y
SR-IOV 0x140 - -
ARI 0x180 0x100 -
Device Serial Number 0x1A0 - -
Secondary PCI Express 0x1C0 - Y
Virtual Channel 0x1F0 - -
Media Configuration Access Port (MCAP) 2 0x350 - -
Address Translation Services 0x380 0x380 -
Page Request 0x390 - -
Data Link Layer Feature 0x3A0 - Y
Physical Layer 16.0 GT/s 0x3B0 - Y
Lane Margining at the Receiver 0x400 - Y
ACS 0x450 0x450 Y
PASID 0x5F0 - -
Configuration Extend Interface 3 Configurable: 0x600 or 0x800 or 0xE00 - -
CCIX Transport DVSEC 0x600 - -
CCIX Protocol DVSEC 0x644 - -
CCIX Protocol Error Message DVSEC 0xDBC - -
  1. Capability might only be present in Function 0.
  2. AMD Vendor Specific Extended Capability (VSEC).
  3. User must add design in PL and connect to hard block.

CPM5 PCIe Extended Configuration Space Capabilities

Table 3. CPM5 PCIe Extended Configuration Space Capabilities Base Address as Endpoint
Extended Capability PF 1 VF RP/Switch Presence
Advanced Error Reporting 0x100 - Y
SR-IOV 0x148 - -
ARI 0x188 0x100 -
Device Serial Number 0x1A0 - -
Secondary PCI Express 0x1C0 - Y
Virtual Channel 0x1F0 - -
Media Configuration Access Port (MCAP) 2 0x350 - -
Address Translation Services 0x380 0x380 -
Page Request 0x390 - -
Data Link Layer Feature 0x3A0 - Y
Physical Layer 16.0 GT/s 0x3B0 - Y
Lane Margining at the Receiver 0x400 - Y
ACS 0x450 0x450 Y
Physical Layer 32.0 GT/s 0x460 - Y
PASID 0x5F0 - -
Configuration Extend Interface(3) (4) 0x600 0x800 0xE00 - -
CCIX Transport DVSEC 0x600 - -
CCIX Protocol DVSEC 0x644 - -
CCIX Protocol Error Message DVSEC 0xDBC - -
  1. Capability might only be present in Function 0.
  2. AMD Vendor Specific Extended Capability (VSEC).
  3. Configuration extend base address is variable; selected at compile time.
  4. User must add design in PL and connect to hard block.

Additional Features

  • Transaction tag scaling as requester and completer
  • Flow control scaling
  • ASPM L0s support (ASPM support for endpoint port types. In Gen1 and Gen2 configurations, ASPM is not supported for other port types)
  • Function level reset