User Mode - 3.4 English

Versal Adaptive SoC CPM Mode for PCI Express Product Guide (PG346)

Document ID
PG346
Release Date
2024-05-30
Version
3.4 English

The user mode method for HSDP-over-PCIe imposes fewer requirements on the hardware design, but it is also slower than management mode and does not allow for debug access to hardened blocks like SYSMON, DDRMC, and IBERT. User mode must employ a PCIe BAR to access a fabric debug hub from the host PC, which bypasses the DPC entirely and does not operate using DTPs. Instead, the host PC uses memory mapped reads and writes to directly access the debug hub to issue and collect debug data. User mode is identical on CPM4 and CPM5 capable devices and it is recommended to use CPM in DMA mode to easily make use of the AXI Bridge Master type for the PCIe BAR required to reach the debug hub. Debug transactions are then routed through the NoC to the fabric, which opens the possibility to use NoC NMU remapping to ensure the PCIe BAR size remains small and the device address map does not become fragmented.

Figure 1. Example Block Diagram for HSDP-over-PCIe User Mode Debug for CPM4/CPM5
Figure 2. Example Minimum Address Map for HSDP-over-PCIe User Mode Debug for CPM4/CPM5