CPM5 Configuration Notes - 3.4 English

Versal Adaptive SoC CPM Mode for PCI Express Product Guide (PG346)

Document ID
PG346
Release Date
2024-05-30
Version
3.4 English

In many cases which might naturally arise from allowed GTYP quad placements and lane ordering, the PCB designer might conclude it is not feasible to meet length, loss, or other signaling requirements while physically implementing lane reversal on the PCB.

This is likely with x16 and x8 link widths, therefore use lane reversal by the IP rather than physically implementing lane reversal on the PCB. With lane reversal by the IP, CPM5 link width selection in CIPS IP configuration GUI must match the PCB designed link width to ensure lane reversal by the IP will function.

For x4 or narrower link widths, the feasibility of physically implementing lane reversal on the PCB is greater, therefore use this approach instead.