Overview - 3.4 English

Versal Adaptive SoC CPM Mode for PCI Express Product Guide (PG346)

Document ID
PG346
Release Date
2024-05-30
Version
3.4 English

The AMD Versal™ device has an integrated debug that resides in the PMC. The integrated debug subsystem includes the test access port (TAP) controller, the Arm® debug access port (DAP) controller, and the debug packet controller (DPC). The DPC receives command packets, referred to as debug and trace packets (DTP), from one or more debug host interfaces, then generates reply packets and transmits them back to the debug host. The Versal device has four debug host interfaces that are connected to the DPC for interaction with external debug hosts.

  • Serial, low-speed JTAG interface attached to the debug access port (DAP) controller
  • Serial, high-speed debug port (HSDP) connected to the Aurora protocol unit
  • Parallel, high-speed PCIe interface with debug protocols connected to the GTY quad transceivers
  • Parallel PL path for potential soft Aurora IP or other debug interface and protocol in the PL

The focus of this appendix is employing the PCIe link as the communication channel with the DPC, referred to as management (mgmt) mode for HSDP-over-PCIe, and user mode for HSDP-over-PCIe, which is a slower and more restrictive mode to enable debug over a PCIe link. For more information about Versal device integrated debug and other communication channels, refer Versal Adaptive SoC Technical Reference Manual (AM011).

There are three primary components that enable HSDP-over-PCIe debug:

  • Host PC HSDP-PCIe driver
  • Host PC hw_server application
  • HSDP-over-PCIe enabled FPGA design

The following figure shows the role of each component when performing debug over PCIe.

Figure 1. HSDP-over-PCIe Hardware and Software Components