| Name | I/O | Width | Description |
|---|---|---|---|
| pcie0_m_axis_cq_tdata pcie1_m_axis_cq_tdata | O | 1024 | Transmit data from the PCIe completer request interface to the user application. |
| pcie0_m_axis_cq_tuser pcie1_m_axis_cq_tuser | O | 465 | This is a set of signals containing sideband information for the TLP being transferred. These signals are valid when pcie(n)_m_axis_cq_tvalid is High. The individual signals in this set are described in the following table. |
| pcie0_m_axis_cq_tlast pcie1_m_axis_cq_tlast | O | 1 | The core asserts this signal in the last beat of a packet to indicate the end of the packet. When a TLP is transferred in a single beat, the core sets this bit in the first beat of the transfer. This output is used only when the straddle option is disabled. When the straddle option is enabled, the core sets this output permanently to 0. |
| pcie0_m_axis_cq_tkeep pcie1_m_axis_cq_tkeep | O | 32 | The assertion of bit i of this bus during a transfer indicates to the
user logic that Dword i of the
pcie(n)_m_axis_cq_tdata bus contains valid data. The core sets this
bit to 1 contiguously for all Dwords starting from the first Dword
of the descriptor to the last Dword of the payload. Thus,
pcie(n)_m_axis_cq_tdata is set to all 1s in all beats of a packet,
except in the final beat when the total size of the packet is not a
multiple of the width of the data bus (both in Dwords). This is true
for both Dword-aligned and 128b address-aligned modes of payload
transfer. The tkeep bits are valid only when straddle is not enabled on the CQ interface. When straddle is enabled, the tkeep bits are permanently set to all 1s in all beats. The user logic must use the is_sop/is_eop signals in the pcie(n)_m_axis_cq_tuser bus in that case to determine the start and end of TLPs transferred over the interface. |
| pcie0_m_axis_cq_tvalid pcie1_m_axis_cq_tvalid | O | 1 | The core asserts this output whenever it is driving valid data on the pcie(n)_m_axis_cq_tdata bus. The core keeps the valid signal asserted during the transfer of a packet. The user application can pace the data transfer using the pcie(n)_m_axis_cq_tready signal. |
| pcie0_m_axis_cq_tready pcie1_m_axis_cq_tready | I | 1 | Activation of this signal by the user logic
indicates to the PCIe core that
the user logic is ready to accept data. Data is transferred across
the interface when both pcie(n)_m_axis_cq_tvalid and
pcie(n)_m_axis_cq_tready are asserted in the same cycle. If the user logic deasserts the ready signal when pcie(n)_m_axis_cq_tvalid is High, the core maintains the data on the bus and keeps the valid signal asserted until the user logic has asserted the ready signal. |
| Bit Index | Name | Width | Description |
|---|---|---|---|
| 127:0 | byte_en | 128 | The user logic can optionally use these byte
enable bits to determine the valid bytes in the payload of a packet
being transferred. The assertion of bit i of this bus during a transfer indicates to the
user logic that byte i of the
pcie(n)_m_axis_cq_tdata bus contains a valid payload byte. This bit
is not asserted for descriptor bytes. Although the byte enables can be generated by user logic from information in the request descriptor (address and length), as well as the settings of the first_be and last_be signals, the user logic has the option of using these signals directly instead of generating them from other interface signals. When the payload size is more than 2 Dwords (8 bytes), the first bits on this bus for the payload are always contiguous. When the payload size is 2 Dwords or less, the first bits might be non-contiguous. For the special case of a zero-length memory write transaction defined by the PCI Express specifications, the byte_en bits are all 0 when the associated 1 Dword payload is transferred. |
| 143:128 | first_be[15:0] | 16 | Byte enables for the first Dword of the payload.
first_be[3:0] reflects the setting of the First Byte Enable bits in
the Transaction-Layer header of the first TLP in this beat;
first_be[7:4] reflects the setting of the First Byte Enable bits in
the Transaction-Layer header of the second TLP in this beat.
first_be[11:8] reflects the setting of the First Byte Enable bits in
the Transaction-Layer header of the third TLP in this beat; and
first_be[15:12] reflects the setting of the First Byte Enable bits
in the Transaction-Layer header of the fourth TLP in this beat. For
Memory Reads and I/O Reads, the 4 bits indicate the valid bytes to
be read in the first Dword. For Memory Writes and I/O Writes, these
bits indicate the valid bytes in the first Dword of the payload. For
Atomic Operations and Messages with a payload, these bits are set to
all 1s. Bits [15:4] of first_be are valid only when straddle is enabled on the CQ interface. When straddle is disabled, these bits are permanently set to 0s. This field is valid in the first beat of a packet. first_be[3:0] is valid when pcie(n)_m_axis_cq_tvalid and is_sop[0] are both asserted High. first_be[7:4] is valid when pcie(n)_m_axis_cq_tvalid and is_sop[1] are both asserted High. first_be[11:8] is valid when pcie(n)_m_axis_cq_tvalid and is_sop[2] are both asserted High. first_be[15:12] is valid when pcie(n)_m_axis_cq_tvalid and is_sop[3] are both asserted High. |
| 159:144 | last_be[15:0] | 16 | Byte enables for the last Dword of the payload.
last_be[3:0] reflects the setting of the Last Byte Enable bits in
the Transaction-Layer header of the first TLP in this beat;
last_be[7:4] reflects the setting of the Last Byte Enable bits in
the Transaction-Layer header of the second TLP in this beat.
last_be[11:8] reflects the setting of the Last Byte Enable bits in
the Transaction-Layer header of the third TLP in this beat; and
last_be[15:12] reflects the setting of the Last Byte Enable bits in
the Transaction-Layer header of the fourth TLP in this beat. For
Memory Reads, the 4 bits indicate the valid bytes to be read in the
last Dword of the block of data. For Memory Writes, these bits
indicate the valid bytes in the ending Dword of the payload. For
Memory Reads and Writes of one DW transfers and zero length
transfers, these bits should be 0s. For Atomic Operations and
Messages with a payload, these bits are set to all 1s. Bits [15:4] of last_be are valid only when straddle is enabled on the CQ interface. When straddle is disabled, these bits are permanently set to 0s. This field is valid in the first beat of a packet. last_be[3:0] is valid when pcie(n)_m_axis_cq_tvalid and is_eop[0] are both asserted High. last_be[7:4] is valid when pcie(n)_m_axis_cq_tvalid and is_eop[1] are both asserted High. last_be[12:8] is valid when pcie(n)_m_axis_cq_tvalid and is_eop[2] are both asserted High. last_be[15:12] is valid when pcie(n)_m_axis_cq_tvalid and is_eop[3] are both asserted High. |
| 163:160 | is_sop[3:0] | 4 | Signals the start of a new TLP in this beat.
These outputs are set in the first beat of a TLP. When straddle is
disabled, only is_sop[0] is valid and is_sop[1] is permanently set
to 0. When straddle is enabled, the settings are as follows:
Use of this signal is optional for the user logic when the straddle option is disabled, because a new TLP always starts in the beat following tlast assertion. |
| 165:164 | is_sop0_ptr[1:0] | 2 | Location of first SOP in the beat:
|
| 167:166 | is_sop1_ptr[1:0] | 2 | Location of second SOP in the beat:
|
| 169:168 | is_sop2_ptr[1:0] | 2 | Location of third SOP in the beat:
|
| 171:170 | is_sop3_ptr[1:0] | 2 | Location of fourth SOP in the beat:
|
| 175:172 | is_eop[3:0] | 4 | Indicates that a TLP is ending in this beat.
These outputs are set in the final beat of a TLP. When straddle is
enabled, the settings are as follows:
The use of this signal is optional for the user logic when the straddle option is not enabled, because tlast Is asserted in the final beat of a TLP. |
| 180:176 | is_eop0_ptr[4:0] | 5 | Offset of the last Dword of the first TLP ending in this beat. This output is valid when is_eop[0] is asserted. |
| 185:181 | is_eop1_ptr[4:0] | 5 | Offset of the last Dword of the second TLP
ending in this beat. This output is valid when is_eop[1] is
asserted. The output is permanently set to 0 when straddle is disabled. |
| 190:186 | is_eop2_ptr[4:0] | 5 | Offset of the last Dword of the third TLP ending in this beat. This
output is valid when is_eop[2] is asserted. The output is permanently set to 0 when straddle is disabled. |
| 195:191 | is_eop3_ptr[4:0] | 5 | Offset of the last Dword of the fourth TLP ending in this beat. This
output is valid when is_eop[3] is asserted. The output is permanently set to 0 when straddle is disabled. |
| 196 | discontinue | 1 | This signal is asserted by the core in the last
beat of a TLP, if it has detected an uncorrectable error while
reading the TLP payload from its internal FIFO memory. The user
application must discard the entire TLP when such an error is
signaled by the core. This signal is never asserted when the TLP has no payload. It is asserted only in the last beat of the payload transfer, that is when is_eop[0] is High. When the straddle option is enabled, the core does not start a second TLP if it has asserted discontinue in a beat. When the core is configured as an Endpoint, the error is also reported by the core to the Root Complex it is attached to, using Advanced Error Reporting (AER). |
| 240:197 | reserved | 44 | These bits are reserved. |
| 368:241 | parity | 128 | Odd parity for the 1024-bit transmit data. Bit i provides the odd parity computed for byte i of pcie(n)_m_axis_cq_tdata. |
| 372:369 | pasid_valid[3:0] | 4 | Indicates PASID TLP 0,1,2,3 is valid based on the bits set. |
| 452:373 | pasid[79:0] | 80 | Every 20 bits indicates PASID TLP Prefix for TLP0,1,2,3 to the user design. |
| 456:453 | pasid_exe_req[3:0] | 4 | Indicates Execute Requested for TLP0,1,2,3. |
| 460:457 | pasid_pmode_req[3:0] | 4 | Indicates Privileged Mode Requested for TLP0,1,2,3 to the user design. |
| 464:461 | poisoned_tlp[3:0] | 4 |
Indicates poisoned bit set on received TLPs. 0000 - No poisoned TLP received 0001 - One poisoned TLP received at location determined by is_sop0_ptr[1:0] 0011 - Two poisoned TLPs received at locations determined by is_sop0_ptr[1:0], is_sop1_ptr[1:0] 0111 - Three poisoned TLPs received at locations determined by is_sop0_ptr[1:0], is_sop1_ptr[1:0] and is_sop2_ptr[1:0] 1111 - Four poisoned TLPs received at locations determined by is_sop0_ptr[1:0], is_sop1_ptr[1:0], is_sop2_ptr[1:0] and is_sop3_ptr[1:0] |