Connecting the Vivado IDE to the hw_server Application for Debug Over PCIe - 3.4 English

Versal Adaptive SoC CPM Mode for PCI Express Product Guide (PG346)

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3.4 English

At this point, the FPGA design has been loaded, the PCIe link has been established, the HSDP-PCIe driver has been compiled and installed with the correct configuration values, and the hw_server application has been started on the debug Host PC. The remaining step is to connect to hw_server and begin connecting to the debug cores to exchange and display debug data.

  1. Launch Vivado.
  2. Select Open Hardware Manager from the Flow Navigator.
  3. In the Hardware Manager, select Open target > Open New Target.
  4. Connect to the hw_server application from the Vivado IDE.
    • If the debug host is remote, in the Hardware Server Settings window, modify the host name field to the remote server that is running hw_server and the port number field, if using the non-default port.
    • If the debug host is local, in the Hardware Server Settings window, select the Local Server option for the Connect to: field.
  5. If successful, a hardware target should be populated for selection, then click through to Finish.
  6. The target device should be in the Hardware window and a probes file can now be specified in the Hardware Device Properties window after opening the hardware target and the debug core data is displayed
    Note: If using mgmt mode for debug, the hard block debug cores are accessible for debug, while only user debug cores are present when using user mode for debug.
  7. If using mgmt mode for debug, a user can connect to the debug host PC through the XSDB application and issue direct AXI reads and writes through the PMC