RESET Placements - 3.4 English

Versal Adaptive SoC CPM Mode for PCI Express Product Guide (PG346)

Document ID
PG346
Release Date
2024-05-30
Version
3.4 English

Allowed placements are shown in the following table. Placements are selected in CIPS IP configuration GUI as part of PS PMC peripheral and I/O configuration selections.

Table 1. Allowed Reset Pin Placements
CPM5 PCIE Controller and Port Type RESET Pin Location Options
0: Endpoint, Switch Ports (Up/Down) PS MIO 18 (Default)
PMC MIO 24
PMC MIO 38
1: Endpoint, Switch Ports (Up/Down) PS MIO 19 (Default)
PS MIO 25
PS MIO 39
0: Root Port PS MIO 0 (Default)
PS MIO 0 – 25
PMC MIO 0 – 51
1: Root Port PS MIO 1 (Default)
PS MIO 0 – 25
PMC MIO 0 – 51
  1. Root port mode can be enabled simultaneously on both controller 0 and controller 1 as long as one of them is in non-DMA mode.