Example Package - 3.4 English

Versal Adaptive SoC CPM Mode for PCI Express Product Guide (PG346)

Document ID
PG346
Release Date
2024-05-30
Version
3.4 English

The provided example package contains a Vivado design already configured and ready to use for simulation. You need not follow the preparation and setup steps outlined in the later portion of the document. Limitation to these designs are that they are prepared for Vivado 2021.2 tool and Questa simulator 2020.2 version. If a different simulator is preferred, you must follow the preparation and setup steps to recreate the necessary simulation scripts for your simulator. To use the design, the files are structured as follows:

  • Vivado Project:
    • Use Vivado 2021.2 build
    • Open p.xpr Vivado project
  • Launching Simulation:
    • Use QuestaSimulator 2020.2 version
    • Vivado generated simulation script is available in the p/p.sim/sim_1/behav/questa directory
    • Launch vsim and execute the following commands within vsim:
      • do board_compile.do
      • do board_elaborate.do
      • do board_simulate.do
Note: In simulation, you might receive warnings from the internal RAMs within CPM5 block indicating that a write/read contention has occurred on multi-port RAMs. This is normal as the contention is resolved separately outside of the RAM blocks. These warnings can be safely ignored.