Limitations for CPM4 and CPM5 - 3.4 English

Versal Adaptive SoC CPM Mode for PCI Express Product Guide (PG346)

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3.4 English

Speed Change Related Issue #1

Repeated speed changes can result in the link not coming up to the intended targeted speed.
A follow-on attempt should bring the link back. In extremely rare scenarios, a full reboot might be required.

Speed Change Related Issue #2

In extremely rare cases repeated link Rate changes might also result in the following:
  1. PCIe access becoming unresponsive.
  2. While traffic is going on in system and PM D3 is also enabled with rate changes, the host might receive completion timeout for the read when the pre-read is done before the PM D3 sequence is targeted to the EP ECAM space.
In the case of PM D3, AMD recommends that any valid EP address be used except ECAM space in the pre-read before initiating PM D3 sequence.

In all other cases, waiting approximately 20 msec after the link rate and before attempting any PCIe access can help.

However, in scenarios where the transaction still does not complete, a full reboot (power cycle and re-programming image) would be required.

Speed Change Related Issue #3

In RP configuration with core clock of 1 GHz, PCIe link rate changes from Gen1/Gen2 to Gen3/Gen4/Gen5, it can fail to reach the intended speed or link can go down in rare cases.
An additional write with value 1 to the Perform Equalization bit in Link Control 3 register on the Root complex PCIe configuration space is required when the rate change is performed to Gen3, Gen4, or Gen5 speeds from Gen1/Gen2.

Link Autonomous Bandwidth Status (LABS) Bit

As a Root Complex when performing the link width/rate changes, the link width change works as expected. However, the PCIe protocol requires a LABS bit which is not getting set after the link width/rate change.
Note: This is an informational bit and does not impact actual functionality.
Ensure the software / application ignores the LABS bit as this is an informational bit and does not impact functionality.
Note: For any application, AMD recommends that you make sure the link is quiesced and no transactions are pending before performing any link rate changes.

Power Management - ASPM L1/L0s/PM D3

  1. Enabling ASPM L0s/ASPM L1 could show correctable errors being reported on the link by both link partners such as, replay timer timeout, replay timer rollover, and receiver error.
  2. A PCIe Endpoint device might also log errors when Configuration PM D3 transition request comes in during non-quiesced traffic mode.
  3. A PCIe Root Port device does not support ASPM L1 or L0s.
  1. It is recommended that the application disables correctable error reporting or ignores correctable errors reported in event of link transitioned to ASPM L0s / ASPM L1.
  2. For transition to D3Hot, software needs to make sure that the link is quiesced. To ensure Memory Write packets are finished, issue a Memory Read request to the same location. When the completion packet is received, it indicates that the link is quiesced and PM D3 request can be issued.

Concurrent MSI-X Capability and MSI Capability

CPM5 cannot be configured at compile time with both MSI-X Internal capability and MSI Capability enabled.
MSI-X External capability is an option and can be enabled concurrently with MSI capability. This will allow software driver to choose which Interrupt capability to enable at run-time.