Configuration Extend Interface - 3.4 English

Versal Adaptive SoC CPM Mode for PCI Express Product Guide (PG346)

Document ID
PG346
Release Date
2024-05-30
Version
3.4 English

The configuration extend interface allows the core to transfer configuration information with the user application when externally implemented configuration registers are implemented. The following table defines the ports in the configuration extend interface of the core.

Note: The pcie0* signals map to PCIe Controller 0 and pcie1* signals map to PCIe Controller 1 in the port descriptions below.
Table 1. Configuration Extend Interface Port Descriptions
Port I/O Width Description
pcie0_cfg_ext_read_received pcie1_cfg_ext_read_received O 1 Configuration Extend Read Received.

The Block asserts this output when it has received a configuration read request from the link.

Set when PCI Express Extended Configuration Space Enable is selected in User Defined Configuration Capabilities in core configuration in the Vivado IDE.

All received configuration reads with pcie(n)_cfg_ext_register_number in the following ranges are considered to be the PCIe Extended Configuration Space:

  • 0xB0 - 0xBF: When Legacy Extended Configuration Space Enable is set in Vivado IP catalog.
  • E00H - FFCH: When Extended Small is selected in the PCI Express Extended Configuration Space Enable option in the IP catalog.
  • 600H - FFCH: When Extended Large is selected in the PCI Express Extended Configuration Space Enable option.

All received configuration reads regardless of address will be indicated by 1 cycle assertion of pcie(n)_cfg_ext_read_received, and valid data is driven on pcie(n)_cfg_ext_register_number and pcie(n)_cfg_ext_function_number.

Only received configuration reads within the aforementioned ranges need to be responded by User Application outside of the IP.

pcie0_cfg_ext_write_received pcie1_cfg_ext_write_received O 1 Configuration Extend Write Received.

The Block asserts this output when it has received a configuration write request from the link.

Set when PCI Express Extended Configuration Space Enable is selected in User Defined Configuration Capabilities in the core configuration in the Vivado IDE.

Data corresponding to all received configuration writes with pcie(n)_cfg_ext_register_number in the range 0xb0-0xbf is presented on pcie(n)_cfg_ext_register_number, pcie(n)_cfg_ext_function_number, pcie(n)_cfg_ext_write_data and pcie(n)_cfg_ext_write_byte_enable.

All received configuration writes with pcie(n)_cfg_ext_register_number in the 0xE80-0xFFF range are presented on pcie(n)_cfg_ext_register_number, pcie(n)_cfg_ext_function_number, pcie(n)_cfg_ext_wrte_data and pcie(n)_cfg_ext_write_byte_enable.

pcie0_cfg_ext_register_number pcie1_cfg_ext_register_number O 10 Configuration Extend Register Number

The 10-bit address of the configuration register being read or written. The data is valid when pcie(n)_cfg_ext_read_received or pcie(n)_cfg_ext_write_received is High.

pcie0_cfg_ext_function_number pcie1_cfg_ext_function_number O

8 in CPM4

16 in CPM5

Configuration Extend Function Number

The function number corresponding to the configuration read or write request. The data is valid when pcie(n)_cfg_ext_read_received or pcie(n)_cfg_ext_write_received is High.

pcie0_cfg_ext_write_data pcie1_cfg_ext_write_data O 32 Configuration Extend Write Data

Data being written into a configuration register. This output is valid when pcie(n)_cfg_ext_write_received is High.

pcie0_cfg_ext_write_byte_enable pcie1_cfg_ext_write_byte_enable O 4 Configuration Extend Write Byte Enable

Byte enables for a configuration write transaction.

pcie0_cfg_ext_read_data pcie1_cfg_ext_read_data I 32 Configuration Extend Read Data

You can provide data from an externally implemented configuration register to the core through this bus. The core samples this data on the next positive edge of the clock after it sets pcie(n)_cfg_ext_read_received High, if you have set pcie(n)_cfg_ext_read_data_valid.

pcie0_cfg_ext_read_data_valid pcie1_cfg_ext_read_data_valid I 1 Configuration Extend Read Data Valid

The user application asserts this input to the core to supply data from an externally implemented configuration register. The core samples this input data on the next positive edge of the clock after it sets pcie(n)_cfg_ext_read_received High. The core expects the assertions of this signal within 262144 ('h4_0000) clock cycles of user clock after receiving the read request on pcie(n)_cfg_ext_read_received signal. If no response is received by this time, the core will send auto-response with 'h0 payload, and the user application must discard the response and terminate that particular request immediately.